diff --git a/# REF02 Precision Voltage Reference.txt b/# REF02 Precision Voltage Reference.txt
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+# REF02 Precision Voltage Reference
+
+REF02 is an 8-pin precision voltage reference IC. It provides a stable 5.0 V reference output with high initial accuracy, low temperature coefficient, and low noise. The output voltage can be adjusted by approximately ±3% using an external trim resistor. It is designed for precision analog systems requiring a reliable voltage reference.
+
+## Usage/Examples
+
+Precision Data Acquisition Systems
+
+Analog-to-Digital Converters (ADC)
+
+Digital-to-Analog Converters (DAC)
+
+Industrial Process Control
+
+Precision Test and Measurement Instruments
+
+Reference Voltage Sources
+
+## Documentation
+
+To know the details of REF02 IC please go through the documentation : [REF02_datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/REF01_02_03.pdf)
+
+## Comments/Notes
+
+Please note this is a precision voltage reference IC intended for applications requiring a highly stable 5 V reference. The device operates from an input supply of 7 V to 40 V and can source up to 10 mA of output current. Proper supply bypassing and PCB layout are recommended to achieve optimum noise performance and long-term stability.
+
+## Contributer
+
+Name: *Sanchi Ramteke*
+Email: *sanchiramteke2008@gmail.com*
+Year: 2026
+Position: Contributor
\ No newline at end of file
diff --git a/#auto_saved_files# b/#auto_saved_files#
new file mode 100644
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--- /dev/null
+++ b/#auto_saved_files#
@@ -0,0 +1 @@
+C:\Users\sanfr\eSim-Workspace\REF01\_autosave-REF01.kicad_sch
diff --git a/74147.cir b/74147.cir
new file mode 100644
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--- /dev/null
+++ b/74147.cir
@@ -0,0 +1,87 @@
+.title KiCad schematic
+U31 Net-_U23-Pad2_ Net-_U31-Pad2_ d_inverter
+U32 Net-_U24-Pad2_ Net-_U32-Pad2_ d_inverter
+U33 Net-_U25-Pad2_ Net-_U33-Pad2_ d_inverter
+U29 Net-_U20-Pad2_ Net-_U29-Pad2_ d_buffer
+U30 Net-_U21-Pad2_ Net-_U30-Pad2_ d_inverter
+U25 Net-_U14-Pad2_ Net-_U25-Pad2_ d_buffer
+U26 Net-_U16-Pad2_ Net-_U26-Pad2_ d_buffer
+U24 Net-_U13-Pad2_ Net-_U24-Pad2_ d_buffer
+U21 Net-_U11-Pad2_ Net-_U21-Pad2_ d_buffer
+U23 Net-_U12-Pad2_ Net-_U23-Pad2_ d_buffer
+U22 Net-_U15-Pad2_ Net-_U22-Pad2_ d_buffer
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter
+U28 Net-_U19-Pad2_ Net-_U28-Pad2_ d_buffer
+U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_buffer
+U17 i6 i7 i8 i9 Net-_U14-Pad1_ Net-_U16-Pad1_ Net-_U17-Pad7_ Net-_U17-Pad8_ adc_bridge_4
+U18 Net-_U17-Pad8_ Net-_U18-Pad2_ d_inverter
+U19 Net-_U17-Pad7_ Net-_U19-Pad2_ d_inverter
+U9 i8 plot_v1
+U8 i7 plot_v1
+U10 i9 plot_v1
+U7 i6 plot_v1
+U35 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U35-Pad3_ d_and
+U34 Net-_U28-Pad2_ Net-_U27-Pad2_ Net-_U34-Pad3_ d_nor
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U4 i1 i2 i3 i4 i5 Net-_U20-Pad1_ Net-_U11-Pad1_ Net-_U15-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ adc_bridge_5
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U5 i4 plot_v1
+U6 i5 plot_v1
+U2 i2 plot_v1
+U3 i3 plot_v1
+U1 i1 plot_v1
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+v3 i3 GND pulse
+v1 i1 GND pulse
+v4 i4 GND pulse
+v5 i5 GND pulse
+v2 i2 GND pulse
+v9 i9 GND pulse
+v7 i7 GND pulse
+v8 i8 GND pulse
+v6 i6 GND pulse
+U38 Net-_U22-Pad2_ Net-_U34-Pad3_ Net-_U38-Pad3_ d_and
+U37 Net-_U31-Pad2_ Net-_U33-Pad2_ Net-_U37-Pad3_ d_and
+U39 Net-_U24-Pad2_ Net-_U33-Pad2_ Net-_U39-Pad3_ d_and
+U40 Net-_U26-Pad2_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_and
+U36 Net-_U31-Pad2_ Net-_U33-Pad2_ Net-_U36-Pad3_ d_and
+U44 Net-_U32-Pad2_ Net-_U22-Pad2_ Net-_U44-Pad3_ d_and
+U41 Net-_U27-Pad2_ Net-_U34-Pad3_ Net-_U41-Pad3_ d_and
+U43 Net-_U32-Pad2_ Net-_U34-Pad3_ Net-_U43-Pad3_ d_and
+U42 Net-_U21-Pad2_ Net-_U31-Pad2_ Net-_U42-Pad3_ d_and
+U45 Net-_U31-Pad2_ Net-_U34-Pad3_ Net-_U45-Pad3_ d_and
+U59 Net-_U35-Pad3_ Net-_U36-Pad3_ Net-_U59-Pad3_ d_and
+U53 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U53-Pad3_ d_and
+U64 Net-_U63-Pad3_ Net-_U53-Pad3_ Net-_U64-Pad3_ d_or
+U63 Net-_U59-Pad3_ Net-_U34-Pad3_ Net-_U63-Pad3_ d_and
+U65 Net-_U58-Pad3_ Net-_U40-Pad3_ Net-_U65-Pad3_ d_or
+U58 Net-_U39-Pad3_ Net-_U34-Pad3_ Net-_U58-Pad3_ d_and
+U68 Net-_U64-Pad3_ Net-_U65-Pad3_ Net-_U68-Pad3_ d_or
+U67 Net-_U60-Pad3_ Net-_U61-Pad3_ Net-_U67-Pad3_ d_or
+U60 Net-_U54-Pad3_ Net-_U55-Pad3_ Net-_U60-Pad3_ d_or
+U54 Net-_U42-Pad3_ Net-_U43-Pad3_ Net-_U54-Pad3_ d_and
+U55 Net-_U44-Pad3_ Net-_U45-Pad3_ Net-_U55-Pad3_ d_and
+U61 Net-_U46-Pad3_ Net-_U47-Pad3_ Net-_U61-Pad3_ d_or
+U70 Net-_U67-Pad3_ Net-_U70-Pad2_ d_inverter
+U66 Net-_U62-Pad3_ Net-_U66-Pad2_ d_inverter
+U62 Net-_U56-Pad3_ Net-_U57-Pad3_ Net-_U62-Pad3_ d_or
+U75 B plot_v1
+U76 A plot_v1
+U74 C plot_v1
+U72 D plot_v1
+U69 Net-_U68-Pad3_ Net-_U41-Pad3_ Net-_U69-Pad3_ d_or
+U71 Net-_U69-Pad3_ Net-_U71-Pad2_ d_inverter
+U73 Net-_U71-Pad2_ Net-_U70-Pad2_ Net-_U66-Pad2_ Net-_U52-Pad3_ A B C D dac_bridge_4
+U56 Net-_U48-Pad3_ Net-_U49-Pad3_ Net-_U56-Pad3_ d_or
+U52 Net-_U28-Pad2_ Net-_U27-Pad2_ Net-_U52-Pad3_ d_nor
+U57 Net-_U50-Pad3_ Net-_U51-Pad3_ Net-_U57-Pad3_ d_or
+U51 Net-_U26-Pad2_ Net-_U34-Pad3_ Net-_U51-Pad3_ d_and
+U49 Net-_U24-Pad2_ Net-_U34-Pad3_ Net-_U49-Pad3_ d_and
+U50 Net-_U25-Pad2_ Net-_U34-Pad3_ Net-_U50-Pad3_ d_and
+U48 Net-_U23-Pad2_ Net-_U34-Pad3_ Net-_U48-Pad3_ d_and
+U46 Net-_U25-Pad2_ Net-_U34-Pad3_ Net-_U46-Pad3_ d_and
+U47 Net-_U26-Pad2_ Net-_U34-Pad3_ Net-_U47-Pad3_ d_and
+.end
diff --git a/74147.cir.out b/74147.cir.out
new file mode 100644
index 000000000..83c713c45
--- /dev/null
+++ b/74147.cir.out
@@ -0,0 +1,298 @@
+.title kicad schematic
+
+* u31 net-_u23-pad2_ net-_u31-pad2_ d_inverter
+* u32 net-_u24-pad2_ net-_u32-pad2_ d_inverter
+* u33 net-_u25-pad2_ net-_u33-pad2_ d_inverter
+* u29 net-_u20-pad2_ net-_u29-pad2_ d_buffer
+* u30 net-_u21-pad2_ net-_u30-pad2_ d_inverter
+* u25 net-_u14-pad2_ net-_u25-pad2_ d_buffer
+* u26 net-_u16-pad2_ net-_u26-pad2_ d_buffer
+* u24 net-_u13-pad2_ net-_u24-pad2_ d_buffer
+* u21 net-_u11-pad2_ net-_u21-pad2_ d_buffer
+* u23 net-_u12-pad2_ net-_u23-pad2_ d_buffer
+* u22 net-_u15-pad2_ net-_u22-pad2_ d_buffer
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u28 net-_u19-pad2_ net-_u28-pad2_ d_buffer
+* u27 net-_u18-pad2_ net-_u27-pad2_ d_buffer
+* u17 i6 i7 i8 i9 net-_u14-pad1_ net-_u16-pad1_ net-_u17-pad7_ net-_u17-pad8_ adc_bridge_4
+* u18 net-_u17-pad8_ net-_u18-pad2_ d_inverter
+* u19 net-_u17-pad7_ net-_u19-pad2_ d_inverter
+* u9 i8 plot_v1
+* u8 i7 plot_v1
+* u10 i9 plot_v1
+* u7 i6 plot_v1
+* u35 net-_u29-pad2_ net-_u30-pad2_ net-_u35-pad3_ d_and
+* u34 net-_u28-pad2_ net-_u27-pad2_ net-_u34-pad3_ d_nor
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u4 i1 i2 i3 i4 i5 net-_u20-pad1_ net-_u11-pad1_ net-_u15-pad1_ net-_u12-pad1_ net-_u13-pad1_ adc_bridge_5
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u5 i4 plot_v1
+* u6 i5 plot_v1
+* u2 i2 plot_v1
+* u3 i3 plot_v1
+* u1 i1 plot_v1
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+v3 i3 gnd pulse(0 5 0 1n 1n 1m 2m)
+v1 i1 gnd pulse(0 5 0 1n 1n 2m 4m)
+v4 i4 gnd pulse(0 5 0 1n 1n 4m 8m)
+v5 i5 gnd pulse(0 5 0 1n 1n 8m 16m)
+v2 i2 gnd pulse(0 5 0 1n 1n 16m 32m)
+v9 i9 gnd pulse(0 5 0 1n 1n 32m 64m)
+v7 i7 gnd pulse(0 5 0 1n 1n 64m 128m)
+v8 i8 gnd pulse(0 5 0 1n 1n 128m 256m)
+v6 i6 gnd pulse(0 5 0 1n 1n 256m 512m)
+* u38 net-_u22-pad2_ net-_u34-pad3_ net-_u38-pad3_ d_and
+* u37 net-_u31-pad2_ net-_u33-pad2_ net-_u37-pad3_ d_and
+* u39 net-_u24-pad2_ net-_u33-pad2_ net-_u39-pad3_ d_and
+* u40 net-_u26-pad2_ net-_u34-pad3_ net-_u40-pad3_ d_and
+* u36 net-_u31-pad2_ net-_u33-pad2_ net-_u36-pad3_ d_and
+* u44 net-_u32-pad2_ net-_u22-pad2_ net-_u44-pad3_ d_and
+* u41 net-_u27-pad2_ net-_u34-pad3_ net-_u41-pad3_ d_and
+* u43 net-_u32-pad2_ net-_u34-pad3_ net-_u43-pad3_ d_and
+* u42 net-_u21-pad2_ net-_u31-pad2_ net-_u42-pad3_ d_and
+* u45 net-_u31-pad2_ net-_u34-pad3_ net-_u45-pad3_ d_and
+* u59 net-_u35-pad3_ net-_u36-pad3_ net-_u59-pad3_ d_and
+* u53 net-_u37-pad3_ net-_u38-pad3_ net-_u53-pad3_ d_and
+* u64 net-_u63-pad3_ net-_u53-pad3_ net-_u64-pad3_ d_or
+* u63 net-_u59-pad3_ net-_u34-pad3_ net-_u63-pad3_ d_and
+* u65 net-_u58-pad3_ net-_u40-pad3_ net-_u65-pad3_ d_or
+* u58 net-_u39-pad3_ net-_u34-pad3_ net-_u58-pad3_ d_and
+* u68 net-_u64-pad3_ net-_u65-pad3_ net-_u68-pad3_ d_or
+* u67 net-_u60-pad3_ net-_u61-pad3_ net-_u67-pad3_ d_or
+* u60 net-_u54-pad3_ net-_u55-pad3_ net-_u60-pad3_ d_or
+* u54 net-_u42-pad3_ net-_u43-pad3_ net-_u54-pad3_ d_and
+* u55 net-_u44-pad3_ net-_u45-pad3_ net-_u55-pad3_ d_and
+* u61 net-_u46-pad3_ net-_u47-pad3_ net-_u61-pad3_ d_or
+* u70 net-_u67-pad3_ net-_u70-pad2_ d_inverter
+* u66 net-_u62-pad3_ net-_u66-pad2_ d_inverter
+* u62 net-_u56-pad3_ net-_u57-pad3_ net-_u62-pad3_ d_or
+* u75 b plot_v1
+* u76 a plot_v1
+* u74 c plot_v1
+* u72 d plot_v1
+* u69 net-_u68-pad3_ net-_u41-pad3_ net-_u69-pad3_ d_or
+* u71 net-_u69-pad3_ net-_u71-pad2_ d_inverter
+* u73 net-_u71-pad2_ net-_u70-pad2_ net-_u66-pad2_ net-_u52-pad3_ a b c d dac_bridge_4
+* u56 net-_u48-pad3_ net-_u49-pad3_ net-_u56-pad3_ d_or
+* u52 net-_u28-pad2_ net-_u27-pad2_ net-_u52-pad3_ d_nor
+* u57 net-_u50-pad3_ net-_u51-pad3_ net-_u57-pad3_ d_or
+* u51 net-_u26-pad2_ net-_u34-pad3_ net-_u51-pad3_ d_and
+* u49 net-_u24-pad2_ net-_u34-pad3_ net-_u49-pad3_ d_and
+* u50 net-_u25-pad2_ net-_u34-pad3_ net-_u50-pad3_ d_and
+* u48 net-_u23-pad2_ net-_u34-pad3_ net-_u48-pad3_ d_and
+* u46 net-_u25-pad2_ net-_u34-pad3_ net-_u46-pad3_ d_and
+* u47 net-_u26-pad2_ net-_u34-pad3_ net-_u47-pad3_ d_and
+a1 net-_u23-pad2_ net-_u31-pad2_ u31
+a2 net-_u24-pad2_ net-_u32-pad2_ u32
+a3 net-_u25-pad2_ net-_u33-pad2_ u33
+a4 net-_u20-pad2_ net-_u29-pad2_ u29
+a5 net-_u21-pad2_ net-_u30-pad2_ u30
+a6 net-_u14-pad2_ net-_u25-pad2_ u25
+a7 net-_u16-pad2_ net-_u26-pad2_ u26
+a8 net-_u13-pad2_ net-_u24-pad2_ u24
+a9 net-_u11-pad2_ net-_u21-pad2_ u21
+a10 net-_u12-pad2_ net-_u23-pad2_ u23
+a11 net-_u15-pad2_ net-_u22-pad2_ u22
+a12 net-_u20-pad1_ net-_u20-pad2_ u20
+a13 net-_u19-pad2_ net-_u28-pad2_ u28
+a14 net-_u18-pad2_ net-_u27-pad2_ u27
+a15 [i6 i7 i8 i9 ] [net-_u14-pad1_ net-_u16-pad1_ net-_u17-pad7_ net-_u17-pad8_ ] u17
+a16 net-_u17-pad8_ net-_u18-pad2_ u18
+a17 net-_u17-pad7_ net-_u19-pad2_ u19
+a18 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u35-pad3_ u35
+a19 [net-_u28-pad2_ net-_u27-pad2_ ] net-_u34-pad3_ u34
+a20 net-_u14-pad1_ net-_u14-pad2_ u14
+a21 [i1 i2 i3 i4 i5 ] [net-_u20-pad1_ net-_u11-pad1_ net-_u15-pad1_ net-_u12-pad1_ net-_u13-pad1_ ] u4
+a22 net-_u16-pad1_ net-_u16-pad2_ u16
+a23 net-_u11-pad1_ net-_u11-pad2_ u11
+a24 net-_u15-pad1_ net-_u15-pad2_ u15
+a25 net-_u13-pad1_ net-_u13-pad2_ u13
+a26 net-_u12-pad1_ net-_u12-pad2_ u12
+a27 [net-_u22-pad2_ net-_u34-pad3_ ] net-_u38-pad3_ u38
+a28 [net-_u31-pad2_ net-_u33-pad2_ ] net-_u37-pad3_ u37
+a29 [net-_u24-pad2_ net-_u33-pad2_ ] net-_u39-pad3_ u39
+a30 [net-_u26-pad2_ net-_u34-pad3_ ] net-_u40-pad3_ u40
+a31 [net-_u31-pad2_ net-_u33-pad2_ ] net-_u36-pad3_ u36
+a32 [net-_u32-pad2_ net-_u22-pad2_ ] net-_u44-pad3_ u44
+a33 [net-_u27-pad2_ net-_u34-pad3_ ] net-_u41-pad3_ u41
+a34 [net-_u32-pad2_ net-_u34-pad3_ ] net-_u43-pad3_ u43
+a35 [net-_u21-pad2_ net-_u31-pad2_ ] net-_u42-pad3_ u42
+a36 [net-_u31-pad2_ net-_u34-pad3_ ] net-_u45-pad3_ u45
+a37 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u59-pad3_ u59
+a38 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u53-pad3_ u53
+a39 [net-_u63-pad3_ net-_u53-pad3_ ] net-_u64-pad3_ u64
+a40 [net-_u59-pad3_ net-_u34-pad3_ ] net-_u63-pad3_ u63
+a41 [net-_u58-pad3_ net-_u40-pad3_ ] net-_u65-pad3_ u65
+a42 [net-_u39-pad3_ net-_u34-pad3_ ] net-_u58-pad3_ u58
+a43 [net-_u64-pad3_ net-_u65-pad3_ ] net-_u68-pad3_ u68
+a44 [net-_u60-pad3_ net-_u61-pad3_ ] net-_u67-pad3_ u67
+a45 [net-_u54-pad3_ net-_u55-pad3_ ] net-_u60-pad3_ u60
+a46 [net-_u42-pad3_ net-_u43-pad3_ ] net-_u54-pad3_ u54
+a47 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u55-pad3_ u55
+a48 [net-_u46-pad3_ net-_u47-pad3_ ] net-_u61-pad3_ u61
+a49 net-_u67-pad3_ net-_u70-pad2_ u70
+a50 net-_u62-pad3_ net-_u66-pad2_ u66
+a51 [net-_u56-pad3_ net-_u57-pad3_ ] net-_u62-pad3_ u62
+a52 [net-_u68-pad3_ net-_u41-pad3_ ] net-_u69-pad3_ u69
+a53 net-_u69-pad3_ net-_u71-pad2_ u71
+a54 [net-_u71-pad2_ net-_u70-pad2_ net-_u66-pad2_ net-_u52-pad3_ ] [a b c d ] u73
+a55 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u56-pad3_ u56
+a56 [net-_u28-pad2_ net-_u27-pad2_ ] net-_u52-pad3_ u52
+a57 [net-_u50-pad3_ net-_u51-pad3_ ] net-_u57-pad3_ u57
+a58 [net-_u26-pad2_ net-_u34-pad3_ ] net-_u51-pad3_ u51
+a59 [net-_u24-pad2_ net-_u34-pad3_ ] net-_u49-pad3_ u49
+a60 [net-_u25-pad2_ net-_u34-pad3_ ] net-_u50-pad3_ u50
+a61 [net-_u23-pad2_ net-_u34-pad3_ ] net-_u48-pad3_ u48
+a62 [net-_u25-pad2_ net-_u34-pad3_ ] net-_u46-pad3_ u46
+a63 [net-_u26-pad2_ net-_u34-pad3_ ] net-_u47-pad3_ u47
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u29 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u24 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u22 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u28 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_4, Ngspice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_5, Ngspice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u59 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u64 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u65 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u68 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u67 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u60 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u61 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u70 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u62 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u69 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u71 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_4, Ngspice Name: dac_bridge
+.model u73 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u56 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u57 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 5e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(i8)
+plot v(i7)
+plot v(i9)
+plot v(i6)
+plot v(i4)
+plot v(i5)
+plot v(i2)
+plot v(i3)
+plot v(i1)
+plot v(b)
+plot v(a)
+plot v(c)
+plot v(d)
+.endc
+.end
diff --git a/74147.kicad_sch b/74147.kicad_sch
new file mode 100644
index 000000000..3712342d3
--- /dev/null
+++ b/74147.kicad_sch
@@ -0,0 +1,3878 @@
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diff --git a/74147.proj b/74147.proj
new file mode 100644
index 000000000..a82c56525
--- /dev/null
+++ b/74147.proj
@@ -0,0 +1 @@
+schematicFile 74147.kicad_sch
diff --git a/74147.raw b/74147.raw
new file mode 100644
index 000000000..287947787
--- /dev/null
+++ b/74147.raw
@@ -0,0 +1,9890 @@
+Title: kicad schematic
+Date: Wed Jul 08 18:37:37 2026
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 27
+No. Points: 365
+Variables:
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+ 1 v(i3) voltage
+ 2 v(i1) voltage
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diff --git a/74147_Previous_Values.xml b/74147_Previous_Values.xml
new file mode 100644
index 000000000..d202910c4
--- /dev/null
+++ b/74147_Previous_Values.xml
@@ -0,0 +1 @@
+pulse0 5 0 1n 1n 1m 2m pulse0 5 0 1n 1n 2m 4m pulse0 5 0 1n 1n 4m 8m pulse0 5 0 1n 1n 8m 16m pulse0 5 0 1n 1n 16m 32m pulse0 5 0 1n 1n 32m 64m pulse0 5 0 1n 1n 64m 128m pulse0 5 0 1n 1n 128m 256m pulse0 5 0 1n 1n 256m 512m d_inverter d_inverter d_inverter d_buffer d_inverter d_buffer d_buffer d_buffer d_buffer d_buffer d_buffer d_inverter d_buffer d_buffer adc_bridge d_inverter d_inverter d_and d_nor d_inverter adc_bridge d_inverter d_inverter d_inverter d_inverter d_inverter d_and d_and d_and d_and d_and d_and d_and d_and d_and d_and d_and d_and d_or d_and d_or d_and d_or d_or d_or d_and d_and d_or d_inverter d_inverter d_or d_or d_inverter dac_bridge d_or d_nor d_or d_and d_and d_and d_and d_and d_and true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 10 5 sec ms ms dc10 zener7.0 C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 1 10 sec ms ms dc9 zener6.5 C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 10 100 sec ms ms dc15 dc1 dc-1 dc-15 zener6.8 C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 1 5 sec sec sec
-
-
-eSim — Electronic Circuit Simulation
-
-
- An Open-Source EDA Tool for Circuit Design, Simulation, Analysis & PCB Design Developed by FOSSEE Team at IIT Bombay
-
-
-
-
-
-
-
-
-
- Features •
- Architecture •
- Installation •
- Project Structure •
- Tech Stack •
- Contributing •
- License
-
-
----
-
-## 📖 About
-
-**eSim** is a free and open-source EDA (Electronic Design Automation) tool for circuit design, simulation, analysis, and PCB design. It is an integrated tool built using open-source software such as **KiCad**, **Ngspice**, **GHDL**, and **Makerchip**, providing a seamless workflow from schematic capture to simulation results.
-
-eSim is designed for electronics engineers, students, educators, and hobbyists who want a powerful yet cost-free alternative to proprietary EDA tools. It supports analog, digital, and **mixed-signal simulations**, including microcontroller integration.
-
-
- 📥 Download: v2.5 Release |
- 📄 Manual: PDF Guide |
- 📚 Docs: ReadTheDocs
-
-
----
-
-## ✨ Features
-
-| Category | Feature | Description |
-|:---------|:--------|:------------|
-| • **Design** | Schematic Capture | Draw circuit schematics using KiCad's schematic editor with eSim's custom symbol libraries |
-| • **Conversion** | KiCad to Ngspice | Convert KiCad schematics to Ngspice-compatible netlists for simulation |
-| • **Simulation** | Ngspice Engine | Run DC, AC, Transient, and other SPICE analyses with real-time interactive plots |
-| • **Analysis** | Waveform Plotting | Visualize simulation results with matplotlib-based Python plots and Ngspice native plots |
-| • **Model Editor** | Device Models | Create and edit SPICE device models (Diodes, BJTs, MOSFETs, JFETs, IGBTs, etc.) |
-| • **Subcircuits** | Subcircuit Builder | Build, manage, and upload reusable subcircuit blocks — **741+ ICs** in `SubcircuitLibrary` |
-| • **Mixed-Signal** | NGHDL Integration | Interface VHDL digital models (via GHDL) with analog Ngspice simulations |
-| • **Verilog** | Makerchip + NgVeri | Use Makerchip IDE for Verilog/TL-Verilog design and convert to Ngspice models |
-| • **PCB** | Layout Design | Design PCB layouts using KiCad's PCB editor with eSim's footprint libraries |
-| • **Converters** | Schematic Import | Convert PSpice and LTSpice schematics/libraries to KiCad-compatible formats |
-| • **Modelica** | Ngspice-to-Modelica | Convert Ngspice netlists to Modelica models for OpenModelica simulation |
-| • **SKY130 PDK** | SkyWater 130nm | Support for SkyWater SKY130 open-source Process Design Kit |
-| • **IHP PDK** | IHP OpenPDK | Integration with IHP SG13G2 open-source PDK for SiGe BiCMOS |
-
----
-
-## 🏗️ Architecture
-
-### High-Level System Architecture
-
-```mermaid
-graph TB
- %% Styling
- classDef ui fill:#2A3F54,stroke:#1ABB9C,stroke-width:2px,color:#fff
- classDef core fill:#3E536C,stroke:#3498DB,stroke-width:2px,color:#fff
- classDef engine fill:#1F2D3D,stroke:#E74C3C,stroke-width:2px,color:#fff
- classDef data fill:#E9F0F5,stroke:#95A5A6,stroke-width:1px,color:#333
-
- subgraph UI ["User Interface (PyQt6)"]
- A[Application Main Window]:::ui
- PE[Project Explorer]:::ui
- DA[Dock Area Workspace]:::ui
- TE[Time Explorer]:::ui
- CON[Console Widget]:::ui
-
- A --> PE & DA & TE & CON
- end
-
- subgraph CORE ["Core Python Modules"]
- K2N[KiCad-to-Ngspice]:::core
- SIM[Ngspice Simulator]:::core
- PLT[Matplotlib Plotter]:::core
- ME[Model Editor]:::core
- SC[Subcircuit Builder]:::core
-
- DA --> K2N & SIM & ME & SC
- end
-
- subgraph INTEGRATION ["Mixed-Signal & External APIs"]
- NGHDL[NGHDL Interface]:::core
- MKR[Makerchip/NgVeri]:::core
- MOD[Modelica Converter]:::core
- CONV[PSpice/LTSpice Converter]:::core
-
- DA --> NGHDL & MKR & MOD & CONV
- end
-
- subgraph ENGINES ["Simulation & EDA Engines"]
- KICAD[KiCad Eeschema]:::engine
- PCB[KiCad Pcbnew]:::engine
- NGSPICE[Ngspice Backend]:::engine
- GHDL[GHDL Simulator]:::engine
- VER[Verilator]:::engine
- OM[OpenModelica]:::engine
- end
-
- %% Data Flow
- XML[(Netlist / XML)]:::data
- RAW[(Raw Data / txt)]:::data
- VHDL[(VHDL Files)]:::data
-
- K2N -- Generates --> XML
- XML -- Consumed by --> NGSPICE
- SIM -- Triggers --> NGSPICE
- NGSPICE -- Outputs --> RAW
- RAW -- Parsed by --> PLT
-
- NGHDL -- Compiles --> VHDL
- VHDL -- Simulated by --> GHDL
- GHDL -- Co-simulates --> NGSPICE
-
- MKR -- Verilog/TL-V --> VER
-
- KICAD -- Schematic --> K2N
- KICAD -- Netlist --> PCB
-```
-
-*For detailed simulation workflows, sub-system operations, and system flowcharts, please refer to our [Architecture & Workflows Guide](ARCHITECTURE.md).*
-
----
-
-## 📂 Project Structure
-
-### Root Directory
-
-| Path | Type | Description |
-|:-----|:-----|:------------|
-| `src/` | 📁 Directory | **Core application source code** — all Python modules for the eSim GUI and backend |
-| `library/` | 📁 Directory | **Component libraries** — device models, KiCad symbols, subcircuits, and PDK data |
-| `nghdl/` | 📁 Directory | **NGHDL module** — Ngspice-GHDL interface for mixed-signal VHDL simulation |
-| `Examples/` | 📁 Directory | **42 example projects** — ready-to-simulate circuits (RC, BJT, Op-Amp, Mixed-Signal, etc.) |
-| `images/` | 📁 Directory | **UI assets** — application icons, toolbar images, logos, and splash screen |
-| `scripts/` | 📁 Directory | **Launch & setup scripts** — shell scripts for Linux installation and launching |
-| `docs/` | 📁 Directory | **Sphinx documentation** — RST files for ReadTheDocs auto-generated developer docs |
-| `code/` | 📁 Directory | **Sphinx autodoc config** — mirrors `src/` structure for API documentation generation |
-| `flatpak/` | 📁 Directory | **Flatpak packaging** — manifest and wrapper scripts for universal Linux distribution |
-| `appimage/` | 📁 Directory | **AppImage packaging** — build scripts for portable Linux AppImage bundles |
-| `docker-launcher/` | 📁 Directory | **Docker support** — Dockerfile, launcher script, and CI workflows for containerized builds |
-| `snap/` | 📁 Directory | **Snap packaging** — `snapcraft.yaml` for building Snap packages |
-| `ihp/` | 📁 Directory | **IHP PDK integration** — install script, `.spiceinit` config, NMOS example, and ngspice latest installer for IHP SG13G2 SiGe BiCMOS PDK |
-| `patches/` | 📁 Directory | **Source patches** — patch files for modifying Ngspice/GHDL behavior in sandboxed environments |
-| `.github/` | 📁 Directory | **GitHub config** — issue templates, PR templates, and CI/CD workflow definitions |
-| `setup.py` | 📄 File | Python package configuration for pip installation |
-| `requirements.txt` | 📄 File | Python dependency list (PyQt6, matplotlib, numpy, scipy, etc.) |
-| `conf.py` | 📄 File | Sphinx documentation configuration |
-| `VERSION` | 📄 File | Current version identifier (`2.5`) |
-| `INSTALL` | 📄 File | Detailed multi-platform installation instructions |
-| `LICENSE` | 📄 File | GNU General Public License v3.0 |
-
-### Source Code (`src/`) — Detailed Module Breakdown
-
-```
-src/
-├── frontEnd/ # GUI & Main Application
-│ ├── Application.py # Main window, toolbar setup, menu actions (960 lines)
-│ ├── DockArea.py # Tabbed dock workspace for editors/simulators (24K)
-│ ├── ProjectExplorer.py # File tree browser for project navigation (20K)
-│ ├── TimeExplorer.py # Project snapshot/version management (8K)
-│ ├── TerminalUi.py # Embedded terminal widget (5K)
-│ └── Workspace.py # Workspace selection dialog (6K)
-│
-├── kicadtoNgspice/ # KiCad-to-Ngspice Conversion Engine
-│ ├── KicadtoNgspice.py # Main conversion controller & UI (41K)
-│ ├── Convert.py # Netlist parsing and SPICE generation (40K)
-│ ├── Analysis.py # Analysis type configuration (DC, AC, Transient) (32K)
-│ ├── DeviceModel.py # Device model parameter handling (56K)
-│ ├── Source.py # Source component configuration (15K)
-│ ├── Processing.py # Netlist processing pipeline (26K)
-│ ├── SubcircuitTab.py # Subcircuit selection in converter (9K)
-│ ├── Microcontroller.py # Microcontroller model support (10K)
-│ ├── Model.py # Model file handling (6K)
-│ └── TrackWidget.py # UI tracking widget (1K)
-│
-├── ngspiceSimulation/ # Simulation Engine & Plotting
-│ ├── NgspiceWidget.py # Ngspice process management & execution (16K)
-│ ├── plot_window.py # matplotlib-based waveform plotter (66K)
-│ ├── plotting_widgets.py # Custom plot controls and widgets (8K)
-│ └── data_extraction.py # Simulation data file parser (11K)
-│
-├── modelEditor/ # SPICE Model Editor
-│ └── ModelEditor.py # GUI for creating/editing device models (33K)
-│
-├── subcircuit/ # Subcircuit Management
-│ ├── Subcircuit.py # Subcircuit manager main window (3K)
-│ ├── newSub.py # Create new subcircuit (3K)
-│ ├── openSub.py # Open existing subcircuit (1K)
-│ ├── uploadSub.py # Upload subcircuit to library (4K)
-│ └── convertSub.py # Subcircuit format conversion (2K)
-│
-├── maker/ # Makerchip & NgVeri Integration
-│ ├── Maker.py # Makerchip IDE integration (23K)
-│ ├── NgVeri.py # Verilog-to-Ngspice model generator (17K)
-│ ├── ModelGeneration.py # Auto model generation pipeline (48K)
-│ ├── createkicad.py # KiCad symbol creation for models (14K)
-│ ├── makerchip.py # Makerchip cloud IDE connector (3K)
-│ └── Appconfig.py # Maker-specific configuration (2K)
-│
-├── converter/ # Schematic Format Converters
-│ ├── pspiceToKicad.py # PSpice schematic importer (5K)
-│ ├── ltspiceToKicad.py # LTSpice schematic importer (6K)
-│ ├── libConverter.py # Library format converter (3K)
-│ ├── LtspiceLibConverter.py # LTSpice library converter (4K)
-│ ├── browseSchematic.py # File browser for schematics (550B)
-│ ├── LTSpiceToKiCadConverter/ # LTSpice conversion engine
-│ └── schematic_converters/ # Additional schematic parsers
-│
-├── ngspicetoModelica/ # 📐 Ngspice-to-Modelica Converter
-│ ├── NgspicetoModelica.py # Core conversion engine (54K)
-│ └── ModelicaUI.py # Modelica converter GUI (10K)
-│
-├── configuration/ # ⚙️ Application Configuration
-│ └── Appconfig.py # Global config, paths, process tracking (4K)
-│
-├── projManagement/ # 📋 Project Management
-│ ├── Kicad.py # KiCad integration (launch schematic/PCB editor) (9K)
-│ ├── Validation.py # Tool and file validation utilities (7K)
-│ ├── Worker.py # Background process/thread management (3K)
-│ ├── newProject.py # New project creation logic (5K)
-│ └── openProject.py # Open existing project logic (3K)
-│
-└── browser/ # 📖 Help & Documentation
- ├── Welcome.py # Welcome screen display (941B)
- └── UserManual.py # User manual viewer (731B)
-```
-
-### Library Directory (`library/`) — Component Libraries
-
-| Path | Description |
-|:-----|:------------|
-| `deviceModelLibrary/` | SPICE device models organized by type: Diode, BJT (Transistor), MOSFET (MOS), JFET, IGBT, LEDs, Switches, Transmission Lines, and user libraries |
-| `kicadLibrary/` | KiCad schematic symbols (`eSim-symbols/`), footprint libraries (`kicad_eSim-Library/`), and project templates |
-| `SubcircuitLibrary/` | **741+ reusable subcircuit ICs** — logic gates, flip-flops, op-amps, regulators, timers, multiplexers, shift registers, comparators, multipliers, PDK-specific IPs, and more (see [Subcircuit Library](#-subcircuit-library) section) |
-| `modelParamXML/` | XML parameter definitions for device model editor forms |
-| `ngspicetoModelica/` | Mapping files for Ngspice-to-Modelica component translation |
-| `browser/` | HTML/resource files for the built-in help browser |
-| `tlv/` | TL-Verilog support files for Makerchip integration |
-
-### NGHDL Module (`nghdl/`) — Mixed-Signal Interface
-
-| Path | Description |
-|:-----|:------------|
-| `src/ngspice_ghdl.py` | Core interface: manages VHDL upload, GHDL compilation, and Ngspice code model creation |
-| `src/model_generation.py` | Generates C code models from VHDL port definitions for Ngspice |
-| `src/createKicadLibrary.py` | Auto-generates KiCad symbols from VHDL entity definitions |
-| `src/ghdlserver/` | GHDL foreign interface server for inter-process communication with Ngspice |
-| `install-nghdl.sh` | Automated installer for NGHDL dependencies (GHDL, Verilator, Ngspice) |
-| `Example/` | Example VHDL models and mixed-signal simulation projects (including **Microwatt NGHDL co-simulation**) |
-
-### IHP PDK Integration (`ihp/`) — SiGe BiCMOS Open PDK
-
-| Path | Description |
-|:-----|:------------|
-| `ihp-install-script.sh` | Automated installer for IHP SG13G2 open-source SiGe BiCMOS PDK |
-| `install-ngspice-latest.sh` | Script to build and install the **latest ngspice** from source (with OSDI support) — requires eSim/NGHDL to be installed first |
-| `.spiceinit` | Pre-configured `.spiceinit` file for IHP-Open-PDK; automatically placed in the home directory after configuration |
-| `example.cir` | NMOS DC test circuit demonstrating IHP PDK SPICE simulation |
-
----
-
-## 🛠️ Tech Stack
-
-| Layer | Technology | Purpose |
-|:------|:-----------|:--------|
-| **Language** |  | Core application logic |
-| **GUI Framework** |  | Desktop GUI (windows, dialogs, toolbars, docks) |
-| **Plotting** |  | Waveform visualization and data plotting |
-| **Numerics** |   | Numerical computation and signal processing |
-| **Schematic & PCB** |  | Schematic capture and PCB layout design |
-| **SPICE Simulation** |  | Analog/mixed-signal circuit simulation engine |
-| **VHDL Simulation** |  | VHDL analysis, compilation, and simulation |
-| **Verilog** |  | Verilog HDL simulation and model generation |
-| **HDL Cloud IDE** |  | Online Verilog/TL-Verilog IDE integration |
-| **Modelica** |  | Multi-domain modeling and simulation |
-| **PDK** |   | SkyWater 130nm & IHP SiGe BiCMOS open-source PDKs |
-| **Packaging** |   | Cross-distribution Linux packaging & containers |
-| **Documentation** |   | Auto-generated developer documentation |
-| **CI/CD** |  | Automated builds, Docker images, and releases |
-
-### Key Python Dependencies
-
-| Package | Version | Purpose |
-|:--------|:--------|:--------|
-| `PyQt6` | ≥ 6.5.0 | GUI framework |
-| `matplotlib` | 3.7.5 | Waveform plotting |
-| `numpy` | 1.24.4 | Numerical computation |
-| `scipy` | 1.10.1 | Scientific computing |
-| `pillow` | 12.2.0 | Image processing |
-| `hdlparse` | 1.0.4 | HDL file parsing |
-| `watchdog` | 4.0.2 | File system monitoring |
-| `pyparsing` | 3.1.4 | Parser building toolkit |
-
----
-
-## 💻 Installation
-
-### Supported Platforms
-
-| Platform | Method | Status |
-|:---------|:-------|:------:|
-| **All Linux** (Fedora, Ubuntu, openSUSE, Arch, etc.) | Flatpak | ✅ Recommended |
-| **Ubuntu** 22.04 / 23.04 / 24.04 LTS | Native Installer | ✅ Supported |
-| **Windows** 8 / 10 / 11 | Windows Installer | ✅ Supported |
-| **Docker** (any OS) | Docker Container | ✅ Supported |
-
-### 🐧 Linux — Flatpak (Recommended for all distributions)
-
-```bash
-# 1. Install Flatpak (if not already installed)
-# Fedora: sudo dnf install flatpak
-# Ubuntu: sudo apt install flatpak
-# openSUSE: sudo zypper install flatpak
-# Arch: sudo pacman -S flatpak
-
-# 2. Add Flathub repository
-flatpak remote-add --if-not-exists flathub https://dl.flathub.org/repo/flathub.flatpakrepo
-
-# 3. Install eSim
-flatpak install flathub org.fossee.eSim
-
-# 4. Run eSim
-flatpak run org.fossee.eSim
-```
-
-> **⚠️ Flatpak Limitations:** NGHDL, Makerchip, and SKY130 PDK are not included in the Flatpak build. For full mixed-signal support, use the Ubuntu native installer.
-
-### 🐧 Ubuntu — Native Installer
-
-```bash
-# 1. Download and extract eSim
-unzip eSim-2.5.zip
-cd eSim-2.5
-
-# 2. Install eSim with all dependencies
-chmod +x install-eSim.sh
-./install-eSim.sh --install
-
-# 3. Run eSim
-esim
-# Or double-click the eSim desktop icon
-```
-
-### 🪟 Windows
-
-1. Download the eSim installer from [esim.fossee.in/downloads](https://esim.fossee.in/downloads)
-2. Disable antivirus temporarily (if required)
-3. **Important:** Remove MinGW/MSYS from the PATH environment variable if previously installed
-4. Run the installer and follow the on-screen instructions
-5. Launch eSim from the Start Menu or desktop shortcut
-
-### 🐋 Docker
-
-Refer to the [Docker Launcher README](docker-launcher/README.md) for instructions on running eSim in a containerized environment.
-
-> **Note:** The Docker image now includes `libreadline-dev` to fix a build issue on recent Ubuntu base images.
-
-### 📦 Build from Source (Flatpak)
-
-```bash
-cd eSim
-flatpak-builder build flatpak/org.fossee.eSim.yml --install --user
-```
-
-> 📖 For comprehensive installation instructions, see the [INSTALL](INSTALL) file.
-
-### ⚗️ IHP PDK — Latest Ngspice from Source
-
-If you need the latest Ngspice with OSDI support for IHP PDK simulations:
-
-```bash
-# Requires eSim/NGHDL to be installed first
-chmod +x ihp/install-ngspice-latest.sh
-./ihp/install-ngspice-latest.sh
-```
-
----
-
-## 🔄 CI/CD & Packaging
-
-| Workflow | File | Purpose |
-|:---------|:-----|:--------|
-| Docker Image Build | `.github/workflows/docker-image.yml` | Builds and publishes the eSim Docker image |
-| Docker Launcher Build | `.github/workflows/docker-launcher-build.yml` | Builds the cross-platform Python launcher |
-| Ubuntu Release | `.github/workflows/release_ubuntu.yml` | Automated Ubuntu `.deb` package builds |
-
-| Packaging Format | Directory | Description |
-|:-----------------|:----------|:------------|
-| Flatpak | `flatpak/` | Universal Linux package via Flathub |
-| AppImage | `appimage/` | Portable single-file Linux executable |
-| Snap | `snap/` | Ubuntu Snap Store package |
-| Docker | `docker-launcher/` | Containerized distribution with GUI forwarding |
-
----
-
-## 📋 Example Projects
-
-eSim ships with **42 ready-to-simulate example projects** in the `Examples/` directory:
-
-
-📂 Click to expand full example list
-
----
-
-## 📦 Subcircuit Library
-
-The `library/SubcircuitLibrary/` directory contains **741+ verified subcircuit models** contributed by the community. These can be directly used in eSim simulations as subcircuit blocks.
-
-
-📂 Click to expand subcircuit categories
-
-> 💡 **Contributing a Subcircuit?** Follow the guidelines in [CONTRIBUTING.md](CONTRIBUTING.md). Each subcircuit should include a `.sub` SPICE file, a KiCad schematic (`.kicad_sch`), and a test circuit (`.cir`).
-
----
-
-## 🤝 Contributing
-
-We welcome contributions from the community! Whether it's bug fixes, new features, documentation improvements, or example circuits — every contribution matters.
-
-### How to Contribute
-
-```mermaid
-flowchart LR
- A["🍴 Fork/eSim.git
- ```
-3. **Create a new branch** for your changes:
- ```bash
- git checkout -b feature/your-feature-name
- ```
-4. **Make your changes** and commit with a descriptive message:
- ```bash
- git add
- git commit -m "Fixes issue # - Brief description of changes"
- ```
-5. **Push** to your fork and **open a Pull Request**:
- ```bash
- git push origin feature/your-feature-name
- ```
-
-> **📌 Guidelines:**
-> - Each PR should reference an existing issue
-> - One commit per pull request (squash if needed)
-> - Follow [PEP 8](https://www.python.org/dev/peps/pep-0008/) code style
-> - Include a commit body describing what you changed and why
-
-For detailed contribution guidelines, see [CONTRIBUTING.md](CONTRIBUTING.md).
-
----
-
-## 👥 Contributors
-
-A huge thank you to all **149+ amazing people** who have contributed to eSim! 🎉
-
-
-
-
-
-
-
-
-149+ contributors and counting! View all contributors →
-
----
-
-## 📞 Contact & Support
-
-| Channel | Link |
-|:--------|:-----|
-| 📧 **Email** | [contact-esim@fossee.in](mailto:contact-esim@fossee.in) |
-| 🌐 **Website** | [esim.fossee.in](https://esim.fossee.in/) |
-| 💬 **Forum** | [forums.fossee.in](https://forums.fossee.in/) |
-| 📞 **Contact Page** | [esim.fossee.in/contact-us](https://esim.fossee.in/contact-us) |
-| 📄 **User Manual** | [eSim Manual v2.5 (PDF)](https://static.fossee.in/esim/manuals/eSim_Manual_2.5.pdf) |
-| 📚 **Developer Docs** | [esim.readthedocs.io](https://esim.readthedocs.io/en/latest/) |
-
----
-
-## 📝 Recent Changes
-
-A summary of notable changes since the last README update (June 2026):
-
-### 🔧 IHP PDK Enhancements (June 2026)
-- Added `ihp/install-ngspice-latest.sh` — a script to build the latest Ngspice from source with OSDI support for IHP PDK users
-- Added `ihp/.spiceinit` — pre-configured Ngspice initialization file for IHP-Open-PDK; the install script now correctly places it in the user's home directory
-- Added `ihp/example.cir` — an NMOS DC test circuit demonstrating IHP PDK simulation
-
-### 🧩 Subcircuit Library Expansion (June–July 2026)
-Over **100 new subcircuit ICs** were contributed and verified, bringing the total to **741+** entries in `library/SubcircuitLibrary/`. Highlights include:
-- **CA-series ICs**: CA3005, CA3018, CA3019, CA3022, CA3028A, CA3036, CA3054 (and moved CA3020, CA3021, etc. from misplaced locations)
-- **MC-series analog ICs**: MC1306_Sub (audio amp), MC1510_sub (RF/IF amp), MC1545_Sub (video amp), MC1550_Sub (RF/IF amp), MC1554_Sub (audio amp), MC1569_Sub (voltage regulator), MC1595_Sub (4-quadrant multiplier), MC1596_Sub (balanced modulator/demodulator)
-- **Analog ICs from PR #604 (Farhana)**: LT1010, vca821, ths4541, ths4303, opa656, lmh6702, cppll, ad834, ad8307, 3bit_flash_adc
-- **Power/control ICs**: L298N (motor driver), IR2110, IR2130 (gate drivers), IP5328P (power bank IC), TP4056 (Li-ion charger), MCP73831 (Li-Po charger), TL494 (PWM controller), TL783, LP2950, LP2951
-- **Voltage regulators**: LM2941, LM7806, MCP1700, TCA965
-- **Op-amps / comparators**: LM2902, LM2904, LM2917, LM1815
-- **SN74-series digital ICs**: SN74AS303/304/305, SN74LS247, SN74LS295B, SN74LS353, SN74LS451, SN74LS461, SN74LS498, SN74S268, SN74S532, SN74S536, SN74278
-- **TTL/CMOS logic**: 74LS112, 74LS150, 74LS298, 74LS379, 74LS399, 74hc589, 74HCT594, CD4095BMS, CD4016, CD4026B, CD4029B, CD4089B, CD4099B, SN54170, MM74C923, LM3914
-- **Additional digital ICs**: 74ls93, 74ls175, 74ls181, 74ls374, 74ls670, 74lv157, DM74ls173, sn74ls244, sn5470, 4024bc
-
-### 🔀 Library Reorganization (July 2026)
-- **PR #591**: Cleaned up misplaced subcircuits — moved `CA3020`, `LM108`, `LM3080`, `MC1496`, `NE556`, `TL03xA`, `UA702M` from a duplicate location into the canonical `library/SubcircuitLibrary/` path
-- **Subcircuit files** from `SUBCKT/` directory moved to `library/SubcircuitLibrary/` (June 2026)
-
-### 🔬 NGHDL — New Microwatt Example (June 2026)
-- Added a **Microwatt NGHDL co-simulation example** in `nghdl/Example/` demonstrating mixed-signal simulation with the open-source Microwatt POWER ISA soft-core processor (via PR #569)
-
-### 🐋 Docker — Build Fix (June 2026)
-- Added `libreadline-dev` to the Dockerfile to resolve a build failure on newer Ubuntu base images
-
-### 🛠️ Bug Fix — Workspace Newline (June 2026)
-- Fixed workspace newline handling issue (PR #469)
-
----
-
-## 📄 License
-
-eSim is licensed under the **GNU General Public License v3.0**. See [LICENSE](LICENSE) for details.
-
-
-
-
- Built with ❤️ by the FOSSEE Team at IIT Bombay
-
-
-
-
-
-
-
-
-
-
-
- ⭐ If you find eSim useful, consider giving it a star on GitHub!
-
+# MC14077B
+
+## Description
+MC14077B is a Quad 2-Input XNOR Gate IC from the CMOS 4000 series. This subcircuit model is created for use in eSim/SPICE simulations.
+
+## Features
+- Quad 2-input XNOR gates
+- CMOS technology
+- Wide operating voltage range
+- Low power consumption
+- High noise immunity
+
+## Files Included
+- MC14077B.lib
+- MC14077B.cir (if applicable)
+- Symbol file (if applicable)
+
+## Usage
+1. Copy the library file to the appropriate eSim library directory.
+2. Include the library in your schematic.
+3. Place the MC14077B component in the circuit.
+4. Run the simulation.
+
+## Testing
+The subcircuit has been tested in eSim and verified for correct XNOR gate functionality.
diff --git a/README.txt b/README.txt
new file mode 100644
index 000000000..8353b5640
--- /dev/null
+++ b/README.txt
@@ -0,0 +1,32 @@
+# REF01 Precision Voltage Reference
+
+REF01 is an 8-pin precision voltage reference IC. It provides a stable 10.0 V reference output with excellent temperature stability, low noise, and high accuracy. The output voltage can be adjusted by approximately ±3% using an external trim resistor. It is widely used in precision analog and measurement applications. :contentReference[oaicite:0]{index=0}
+
+## Usage/Examples
+
+Precision Data Acquisition Systems
+
+Analog-to-Digital Converters (ADC)
+
+Digital-to-Analog Converters (DAC)
+
+Industrial Process Control
+
+Precision Test and Measurement Instruments
+
+Reference Voltage Sources
+
+## Documentation
+
+To know the details of REF01 IC please go through the documentation : https://www.analog.com/media/en/technical-documentation/data-sheets/REF01_02_03.pdf :contentReference[oaicite:1]{index=1}
+
+## Comments/Notes
+
+Please note this is a precision voltage reference IC intended for applications requiring a highly stable reference voltage. The device operates from an input supply of 12 V to 36 V and provides a fixed 10 V output with up to 10 mA load current. Proper supply bypassing and PCB layout are recommended to achieve optimum noise performance and stability. :contentReference[oaicite:2]{index=2}
+
+## Contributer
+
+Name: *Sanchi Ramteke*
+Email: *sanchiramteke2008@gmail.com*
+Year: 2026
+Position: Contributor
\ No newline at end of file
diff --git a/REF01.cir b/REF01.cir
new file mode 100644
index 000000000..c09377cdb
--- /dev/null
+++ b/REF01.cir
@@ -0,0 +1,52 @@
+.title KiCad schematic
+Q16 Net-_I1-Pad2_ Net-_I1-Pad2_ Net-_Q16-Pad3_ eSim_NPN
+R12 GND Net-_Q15-Pad3_ 10k
+Q15 Net-_Q13-Pad2_ Net-_I1-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R13 GND Net-_Q16-Pad3_ 10k
+R16 GND q19 10k
+Q9 Net-_Q7-Pad3_ Net-_C1-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+Q8 Net-_Q5-Pad3_ Net-_I1-Pad2_ Net-_Q8-Pad3_ eSim_NPN
+R9 GND Net-_Q8-Pad3_ 10k
+R6 Net-_R4-Pad2_ Net-_Q3-Pad3_ 1k
+R7 GND Net-_R4-Pad2_ 10k
+R4 GND Net-_R4-Pad2_ 10k
+Q6 Net-_Q11-Pad2_ Net-_Q10-Pad1_ Net-_Q6-Pad3_ eSim_PNP
+R8 Net-_Q6-Pad3_ input 10k
+R5 Net-_Q3-Pad1_ Net-_D1-Pad2_ 16k
+Q4 Net-_Q11-Pad2_ Net-_D1-Pad2_ Net-_Q4-Pad3_ eSim_NPN
+D1 output Net-_D1-Pad2_ eSim_Diode
+Q1 Net-_C1-Pad2_ Net-_Q1-Pad2_ e eSim_NPN
+R2 Net-_C1-Pad2_ Net-_D1-Pad2_ 51k
+U1 e plot_v1
+Q2 Net-_C1-Pad2_ Net-_Q1-Pad2_ e eSim_NPN
+R1 Net-_Q3-Pad3_ e 1.79k
+U2 q19 plot_v1
+Q5 Net-_Q4-Pad3_ Net-_Q3-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+R3 Net-_Q1-Pad2_ q19 17k
+Q3 Net-_Q3-Pad1_ q19 Net-_Q3-Pad3_ eSim_NPN
+C2 output GND 0.1u
+R17 unconnected-_R17-Pad1_ q19 100k
+R15 q19 output 73k
+R11 Net-_Q13-Pad3_ input 10k
+Q13 dv1 Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_PNP
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q17 Net-_Q13-Pad3_ input Net-_Q17-Pad3_ eSim_NPN
+Q14 Net-_Q13-Pad2_ Net-_Q13-Pad2_ input eSim_PNP
+R10 Net-_Q10-Pad3_ input 10k
+Q11 Net-_C1-Pad1_ Net-_Q11-Pad2_ Net-_Q10-Pad1_ eSim_PNP
+I1 input Net-_I1-Pad2_ 50u
+Q7 Net-_C1-Pad1_ Net-_D1-Pad2_ Net-_Q7-Pad3_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p
+D3 dv2 Net-_D3-Pad2_ eSim_Diode
+U4 dv1 plot_v1
+Q12 GND Net-_C1-Pad1_ Net-_D3-Pad2_ eSim_PNP
+U3 dv2 plot_v1
+D2 dv1 dv2 eSim_Diode
+U6 input plot_v1
+R14 Net-_Q17-Pad3_ input 1k
+Q19 Net-_Q17-Pad3_ Net-_Q18-Pad3_ output eSim_NPN
+Q18 Net-_Q17-Pad3_ dv1 Net-_Q18-Pad3_ eSim_NPN
+v1 input GND DC
+U5 output plot_v1
+C3 input GND 0.1u
+.end
diff --git a/REF01.cir.out b/REF01.cir.out
new file mode 100644
index 000000000..cb819ca54
--- /dev/null
+++ b/REF01.cir.out
@@ -0,0 +1,70 @@
+.title kicad schematic
+
+.include PNP.lib
+.include D.lib
+.include NPN.lib
+q16 net-_i1-pad2_ net-_i1-pad2_ net-_q16-pad3_ Q2N2222
+r12 gnd net-_q15-pad3_ 10k
+q15 net-_q13-pad2_ net-_i1-pad2_ net-_q15-pad3_ Q2N2222
+r13 gnd net-_q16-pad3_ 10k
+r16 gnd q19 10k
+q9 net-_q7-pad3_ net-_c1-pad2_ net-_q5-pad3_ Q2N2222
+q8 net-_q5-pad3_ net-_i1-pad2_ net-_q8-pad3_ Q2N2222
+r9 gnd net-_q8-pad3_ 10k
+r6 net-_r4-pad2_ net-_q3-pad3_ 1k
+r7 gnd net-_r4-pad2_ 10k
+r4 gnd net-_r4-pad2_ 10k
+q6 net-_q11-pad2_ net-_q10-pad1_ net-_q6-pad3_ Q2N2907A
+r8 net-_q6-pad3_ input 10k
+r5 net-_q3-pad1_ net-_d1-pad2_ 16k
+q4 net-_q11-pad2_ net-_d1-pad2_ net-_q4-pad3_ Q2N2222
+d1 output net-_d1-pad2_ 1N4148
+q1 net-_c1-pad2_ net-_q1-pad2_ e Q2N2222
+r2 net-_c1-pad2_ net-_d1-pad2_ 51k
+* u1 e plot_v1
+q2 net-_c1-pad2_ net-_q1-pad2_ e Q2N2222
+r1 net-_q3-pad3_ e 1.79k
+* u2 q19 plot_v1
+q5 net-_q4-pad3_ net-_q3-pad1_ net-_q5-pad3_ Q2N2222
+r3 net-_q1-pad2_ q19 17k
+q3 net-_q3-pad1_ q19 net-_q3-pad3_ Q2N2222
+c2 output gnd 0.1u
+r17 unconnected-_r17-pad1_ q19 100k
+r15 q19 output 73k
+r11 net-_q13-pad3_ input 10k
+q13 dv1 net-_q13-pad2_ net-_q13-pad3_ Q2N2907A
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ Q2N2907A
+q17 net-_q13-pad3_ input net-_q17-pad3_ Q2N2222
+q14 net-_q13-pad2_ net-_q13-pad2_ input Q2N2907A
+r10 net-_q10-pad3_ input 10k
+q11 net-_c1-pad1_ net-_q11-pad2_ net-_q10-pad1_ Q2N2907A
+i1 input net-_i1-pad2_ 50u
+q7 net-_c1-pad1_ net-_d1-pad2_ net-_q7-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+d3 dv2 net-_d3-pad2_ 1N4148
+* u4 dv1 plot_v1
+q12 gnd net-_c1-pad1_ net-_d3-pad2_ Q2N2907A
+* u3 dv2 plot_v1
+d2 dv1 dv2 1N4148
+* u6 input plot_v1
+r14 net-_q17-pad3_ input 1k
+q19 net-_q17-pad3_ net-_q18-pad3_ output Q2N2222
+q18 net-_q17-pad3_ dv1 net-_q18-pad3_ Q2N2222
+v1 input gnd dc 15
+* u5 output plot_v1
+c3 input gnd 0.1u
+.tran 10e-03 20e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(e)
+plot v(q19)
+plot v(dv1)
+plot v(dv2)
+plot v(input)
+plot v(output)
+.endc
+.end
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new file mode 100644
index 000000000..041a66b74
--- /dev/null
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+ (reference "U3") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/f12c29f6-a2e1-4598-82f9-6e674ff4a749"
+ (reference "U4") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/8516dfed-8616-40bd-9e0f-1f4622e71c09"
+ (reference "U5") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/7c7894f5-7e0b-4cd1-81e7-4fe7706d23eb"
+ (reference "U6") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/a0e98819-8922-4fcf-82da-99acaff2b0f4"
+ (reference "v1") (unit 1) (value "DC") (footprint "R1")
+ )
+ )
+)
diff --git a/REF01.proj b/REF01.proj
new file mode 100644
index 000000000..85700be28
--- /dev/null
+++ b/REF01.proj
@@ -0,0 +1 @@
+schematicFile REF01.kicad_sch
diff --git a/REF01.raw b/REF01.raw
new file mode 100644
index 000000000..d1c371f69
--- /dev/null
+++ b/REF01.raw
@@ -0,0 +1,3068 @@
+Title: kicad schematic
+Date: Tue Jul 07 10:19:47 2026
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 51
+No. Points: 59
+Variables:
+ 0 time time
+ 1 v(net-_i1-pad2_) voltage
+ 2 v(net-_q16-pad3_) voltage
+ 3 v(net-_q15-pad3_) voltage
+ 4 v(net-_q13-pad2_) voltage
+ 5 v(q19) voltage
+ 6 v(net-_q7-pad3_) voltage
+ 7 v(net-_c1-pad2_) voltage
+ 8 v(net-_q5-pad3_) voltage
+ 9 v(net-_q8-pad3_) voltage
+ 10 v(net-_r4-pad2_) voltage
+ 11 v(net-_q3-pad3_) voltage
+ 12 v(net-_q11-pad2_) voltage
+ 13 v(net-_q10-pad1_) voltage
+ 14 v(net-_q6-pad3_) voltage
+ 15 v(input) voltage
+ 16 v(net-_q3-pad1_) voltage
+ 17 v(net-_d1-pad2_) voltage
+ 18 v(net-_q4-pad3_) voltage
+ 19 v(output) voltage
+ 20 v(net-_q1-pad2_) voltage
+ 21 v(e) voltage
+ 22 v(unconnected-_r17-pad1_) voltage
+ 23 v(net-_q13-pad3_) voltage
+ 24 v(dv1) voltage
+ 25 v(net-_q10-pad3_) voltage
+ 26 v(net-_q17-pad3_) voltage
+ 27 v(net-_c1-pad1_) voltage
+ 28 v(dv2) voltage
+ 29 v(net-_d3-pad2_) voltage
+ 30 v(net-_q18-pad3_) voltage
+ 31 v(q12#collCX) voltage
+ 32 v(q11#collCX) voltage
+ 33 v(q14#collCX) voltage
+ 34 v(q10#collCX) voltage
+ 35 v(q13#collCX) voltage
+ 36 v(q6#collCX) voltage
+ 37 v(q18#collCX) voltage
+ 38 v(q19#collCX) voltage
+ 39 v(q7#collCX) voltage
+ 40 v(q17#collCX) voltage
+ 41 v(q3#collCX) voltage
+ 42 v(q5#collCX) voltage
+ 43 v(q2#collCX) voltage
+ 44 v(q1#collCX) voltage
+ 45 v(q4#collCX) voltage
+ 46 v(q8#collCX) voltage
+ 47 v(q9#collCX) voltage
+ 48 v(q15#collCX) voltage
+ 49 v(q16#collCX) voltage
+ 50 i(v1) current
+Values:
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diff --git a/REF01_Previous_Values.xml b/REF01_Previous_Values.xml
new file mode 100644
index 000000000..55878631f
--- /dev/null
+++ b/REF01_Previous_Values.xml
@@ -0,0 +1 @@
+50u dc15 C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 10 20 sec ms ms dc15 50u 100u 5u 100n 100 10 1 5 7 6 6.5 6.2 6.24 6.25 20u C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts 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d_or d_and d_and d_buffer d_nor d_nand d_nand d_nor d_nand d_nor d_nand adc_bridge d_inverter d_nor adc_bridge true false false Hz Hz 0 Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes Volts or Amperes 0 10 5 sec ms ms sine0 0.05 1000 0 0 dc9 sine0 9 1000 0 0 C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib true false false Hz Hz V1 0 0.1 12 0 Volts or Amperes Volts or Amperes Volts or Amperes V2 0 0.1 12 Volts or Amperes Volts or Amperes Volts or Amperes 10 100 15 ms us ms 
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