diff --git a/Documentation/core-api/drivers.rst b/Documentation/core-api/drivers.rst index fcea7a81..5d21f777 100644 --- a/Documentation/core-api/drivers.rst +++ b/Documentation/core-api/drivers.rst @@ -32,6 +32,10 @@ drivers/ 按 console、tty、video、storage、net、input、usb、sound 等设 - ``e1000e`` - Intel 82574L/82574IT、82583V PCIe 千兆网卡；共用单 eth0 服务， 不替换已有网络 owner。设备范围和验证边界见 :doc:`e1000e`。 + * - ``R8169`` + - ``r8169`` + - Realtek RTL8111/8168 千兆与 RTL8125 2.5GbE PCIe 网卡；共用单 eth0 + 服务。芯片版本、固件来源和验证范围见 :doc:`realtek`。 * - ``MOUSE_PS2`` / ``USB_UHCI_HCD`` - ``mouse`` / ``uhci`` - PS/2、VMware 鼠标与 UHCI HID；键盘基础输入和分发入口内置。 diff --git a/Documentation/core-api/index.rst b/Documentation/core-api/index.rst index bce1a16a..b1e856de 100644 --- a/Documentation/core-api/index.rst +++ b/Documentation/core-api/index.rst @@ -17,5 +17,6 @@ resource-limits drivers e1000e + realtek usb svga diff --git a/Documentation/core-api/realtek.rst b/Documentation/core-api/realtek.rst new file mode 100644 index 00000000..31ac55c6 --- /dev/null +++ b/Documentation/core-api/realtek.rst @@ -0,0 +1,113 @@ +========================== +Realtek PCIe 以太网驱动 +========================== + +设备与配置 +========== + +``drivers/net/r8169/`` 提供 ReliefNT 原生网卡驱动。``CONFIG_R8169`` 为 +tristate，``make defconfig`` 默认选择 ``y``。选择 ``m`` 生成 +``drivers/net/r8169/r8169.ko``，由普通 ``modprobe`` 根据 PCI 别名加载。 + +设备表包含 ``10ec:8168`` 和 ``10ec:8125``。驱动进一步读取 TxConfig +中的硬件版本，分别选择初始化、PHY 和固件流程。 + +.. list-table:: 已实现的芯片版本路径 + :header-rows: 1 + :widths: 30 70 + + * - PCI ID + - MAC 版本 + * - ``10ec:8168`` + - RTL8111/8168 B、C、CP、D、DP、E、E-VL、F、G、GU、H、EP、FP。 + 按 OpenBSD 的版本掩码区分家族与 B/C 的 spin。 + * - ``10ec:8125`` + - RTL8125A ``0x60900000``、B ``0x64100000``、D-1 ``0x68800000``、 + D-2 ``0x68900000``。 + +未知 MAC 家族返回 ``-ENODEV``。现有网络服务仅提供一个外部 Ethernet +接口，先注册的网卡拥有 ``eth0``，后来的 owner 收到 ``-EBUSY``。 +驱动复用内部历史名称 ``register_e1000`` 的服务，网络用户程序继续使用 +现有 Linux socket、ioctl、netlink 和 proc 接口。 + +.. code-block:: sh + + modinfo r8169 + modprobe r8169 + ip link show eth0 + ip addr show dev eth0 + cat /proc/net/dev + rmmod r8169 + +无网线时接口仍可查询和配置，载波状态来自硬件。PHY 自动协商覆盖 +10/100/1000 Mb/s，RTL8125 另行通告 2500BASE-T 全双工。协商异步完成。 +PHY、EPHY、CSI、固件握手和复位均有界等待，失败返回具体 errno。 + +硬件初始化中的微秒级稳定等待使用启动时间采样；短于 1 ms 的等待最多 +轮询 4096 次，且采样期间关闭本地中断以避免 CPU 迁移。时钟停滞、回退或 +达到轮询上限时改用 tick 等待；较长等待也使用 tick 等待，并额外加入一整个 +tick，以覆盖请求恰好接近下一个 tick 的情况。等待返回后恢复原中断状态， +调用方不得持有自旋锁。短等待依赖内核启动时钟的精度；该时钟突然向前跳变 +可能缩短等待。 + +收发和生命周期 +============== + +驱动优先映射 PCI BAR2，再尝试其他有效内存 BAR，支持 64 位地址。 +PCI 电源管理使用常规 capability 链请求 D0。原始 MAC 在复位前读取并保留， +无效地址导致初始化失败。 +早期 RTL8168 的控制 BAR 可能只有 256 字节，此时可通过该设备的 I/O BAR +访问同一寄存器组。PCI 内存映射仍要求完整页面位于有效 BAR 内。 + +RX/TX 各使用 256 个 16 字节经典描述符和 2048 字节缓冲区。RTL8125 +显式选择经典布局。描述符保留物理 DMA 地址，CPU 通过独立映射访问数据。 +所有权交接使用 acquire/release 屏障，发送与接收有独立的短临界区。 +当前使用单队列轮询，MTU 为 1500，IP/传输层校验和由现有网络栈计算。 + +发送帧补零到最小 Ethernet 长度，再由硬件附加 FCS。队列满返回 +``-EAGAIN``。接收检查错误、缓冲区与调用者容量，移除一个 FCS，并完整 +丢弃跨描述符的异常分片链。接收过滤器接受本站单播、广播和多播，供 +IPv4 ARP、DHCP 与 IPv6 邻居发现使用。 + +初始化先禁用 PCI bus master 并确认控制器复位，再分配和发布 DMA 队列。 +卸载由模块 owner 关闭回调准入、排空在途调用，随后停止收发和复位。 +停止失败时保留 DMA、MMIO 和模块代码以供重试。释放内存后 PCI bus master +保持关闭。 + +固件和许可 +========== + +RTL8125 的 MAC/PHY 固件以未经修改的常量寄存器对嵌入内核或模块，启动时 +按芯片版本选择。构建消费仓库内数据。运行时无需网络下载。 +固件在完成写入与握手后才更新版本标记，并回读确认。 + +硬件初始化改编自 OpenBSD src 提交 +``7779d12194498048b288afda664dd6271a2ec016``。 +RTL8111/8168 派生代码保留 BSD-4-Clause，RTL8125 派生代码保留 ISC， +固件保留 Realtek 的再分发许可。项目新增的 PCI/DMA/模块连接代码使用 +Apache-2.0。完整声明见 ``NOTICE`` 和 ``LICENSES/realtek/``。 +``modules_install`` 将声明放入版本化模块目录的 ``LICENSES/``，连同 +模块加入安装所有权和校验清单，并随 ReliefOS 的内核载荷分发。 + +This product includes software developed by Bill Paul. + +* `OpenBSD re.c `_ +* `OpenBSD if_rge.c `_ +* `Realtek 固件数据与许可 `_ +* `Realtek 提交的 RTL8125 DPDK 寄存器与描述符定义 `_ + +验证范围 +======== + +``tools/test_r8169.py`` 编译真实驱动对象并模拟 PCI/MMIO/DMA 边界，另行编译 +真实寄存器与等待实现，检查时钟边界、中断状态和不同寄存器访问方式。 +它覆盖 4 GiB 以上地址、收发回绕、长度与错误检查、补零、无载波、资源分配 +失败、owner 冲突、停止失败保留与重试。芯片模型覆盖四个 RTL8125 版本和 +RTL8168 家族路径。真实 PHY 协商、DMA 时序和实体网线收发仍需对应硬件验证。 + +本次 QEMU 回归覆盖默认内置启动，以及无匹配 Realtek 硬件时三次 +``r8169.ko`` 加载与卸载。既有 e1000 的 IPv4、IPv6 ping 均通过。 +测试使用当前新编译内核和私有 initramfs，BusyBox 来自已有 ReliefOS 构建。 + +本地 QEMU 只提供 RTL8139 Realtek 模型，真实 RTL8111/8168、RTL8125 +需要实体网卡或正确的 PCI 直通验证。实体网卡验证未完成。VMware 验证未完成。 diff --git a/LICENSES/realtek/OpenBSD-BSD-4-Clause.txt b/LICENSES/realtek/OpenBSD-BSD-4-Clause.txt new file mode 100644 index 00000000..0d94d71a --- /dev/null +++ b/LICENSES/realtek/OpenBSD-BSD-4-Clause.txt @@ -0,0 +1,37 @@ +The RTL8168 initialization and PHY register sequences are adapted from +OpenBSD re.c, rtl81x9reg.h and rgephy.c, at commit +7779d12194498048b288afda664dd6271a2ec016. + +Copyright (c) 1997, 1998-2003 + Bill Paul . All rights reserved. +Copyright (c) 1997, 1998 + Bill Paul . All rights reserved. +Copyright (c) 2003 + Bill Paul . All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. All advertising materials mentioning features or use of this software + must display the following acknowledgement: + This product includes software developed by Bill Paul. +4. Neither the name of the author nor the names of any co-contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD +BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +THE POSSIBILITY OF SUCH DAMAGE. diff --git a/LICENSES/realtek/OpenBSD-ISC.txt b/LICENSES/realtek/OpenBSD-ISC.txt new file mode 100644 index 00000000..cdda680a --- /dev/null +++ b/LICENSES/realtek/OpenBSD-ISC.txt @@ -0,0 +1,14 @@ +Copyright (c) 2019, 2020, 2023-2026 + Kevin Lo + +Permission to use, copy, modify, and distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/LICENSES/realtek/Realtek-firmware.txt b/LICENSES/realtek/Realtek-firmware.txt new file mode 100644 index 00000000..4128c0e4 --- /dev/null +++ b/LICENSES/realtek/Realtek-firmware.txt @@ -0,0 +1,15 @@ +Copyright (c) 2026 Realtek Semiconductor Corporation + +Permission is hereby granted for the distribution of this firmware +data in hexadecimal or equivalent format, provided this copyright +notice is accompanying it. + +Copyright (c) 2011-2013, Realtek Semiconductor Corporation + +Permission is hereby granted for the distribution of this firmware +data in hexadecimal or equivalent format, provided this copyright +notice is accompanying it. + +Embedded, unchanged register-pair data for RTL8125 A/B/D-1/D-2. +Source: OpenBSD src sys/dev/microcode/rge/rgemcode.h +Revision: 7779d12194498048b288afda664dd6271a2ec016 diff --git a/NOTICE b/NOTICE index f6a4f020..e4377ed6 100644 --- a/NOTICE +++ b/NOTICE @@ -32,6 +32,20 @@ Third-party components in this repository drivers/video/framebuffer/framebuffer.c (see the ReliefNT rules in Kbuild). * zlib 1.3.2 puff (third_party/zlib/contrib/puff/puff.c): zlib License. See third_party/zlib/LICENSE. Copyright (C) 2002-2013 Mark Adler. +* Realtek PCIe Ethernet hardware support in drivers/net/r8169/: + RTL8111/8168 register/PHY sequences are adapted from OpenBSD re.c, + rtl81x9reg.h and rgephy.c under Bill Paul's BSD-4-Clause terms. + This product includes software developed by Bill Paul. + RTL8125 initialization is adapted from OpenBSD if_rge.c and if_rgereg.h + under Kevin Lo's ISC terms. The pinned OpenBSD src revision is + 7779d12194498048b288afda664dd6271a2ec016. + Complete notices and conditions are in LICENSES/realtek/OpenBSD-ISC.txt + and LICENSES/realtek/OpenBSD-BSD-4-Clause.txt and in the derived source. + Embedded RTL8125 firmware register pairs are unchanged data from + sys/dev/microcode/rge/rgemcode.h at that revision, copyright (c) 2026 + Realtek Semiconductor Corporation, under its accompanying firmware + redistribution permission. See LICENSES/realtek/Realtek-firmware.txt. + The firmware data and derived files retain their respective terms. * Linux kernel 6.12 build and configuration infrastructure (selected files in scripts/basic/, scripts/include/, scripts/kconfig/, scripts/Makefile.*, scripts/Kbuild.include, and scripts/subarch.include): sourced from the diff --git a/drivers/net/Kbuild b/drivers/net/Kbuild index cad904f1..816b90ac 100644 --- a/drivers/net/Kbuild +++ b/drivers/net/Kbuild @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 # Objects are owned by this directory; child modules own their own lists. -obj-y := e1000/ e1000e/ +obj-y := e1000/ e1000e/ r8169/ include $(srctree)/scripts/Makefile.module diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3dd3db1e..c68e9ca2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2,4 +2,5 @@ menu "Network device drivers" source "drivers/net/e1000/Kconfig" source "drivers/net/e1000e/Kconfig" +source "drivers/net/r8169/Kconfig" endmenu diff --git a/drivers/net/r8169/Kbuild b/drivers/net/r8169/Kbuild new file mode 100644 index 00000000..d6c9a917 --- /dev/null +++ b/drivers/net/r8169/Kbuild @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +obj-$(CONFIG_R8169) += r8169.o +r8169-y := main.o hardware.o io.o rings.o rtl8168.o rtl8125.o firmware_8125.o module.o + +include $(srctree)/scripts/Makefile.module diff --git a/drivers/net/r8169/Kconfig b/drivers/net/r8169/Kconfig new file mode 100644 index 00000000..da708d32 --- /dev/null +++ b/drivers/net/r8169/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +config R8169 + tristate "Realtek RTL8111/8168 and RTL8125 PCIe Ethernet" + default y + help + Native driver for supported Realtek RTL8111/8168 Gigabit and RTL8125 + 2.5 Gigabit PCIe Ethernet MAC revisions. Supports coherent DMA and + standard copper autonegotiation, with software protocol checksums. + Select M to build r8169.ko. The default configuration builds it in. diff --git a/drivers/net/r8169/firmware_8125.c b/drivers/net/r8169/firmware_8125.c new file mode 100644 index 00000000..7c51d49d --- /dev/null +++ b/drivers/net/r8169/firmware_8125.c @@ -0,0 +1,2548 @@ +/* $OpenBSD: rgemcode.h,v 1.2 2026/10/27 01:38:20 kevlo Exp $ */ + +/* + * Copyright (c) 2026 Realtek Semiconductor Corporation + * + * Permission is hereby granted for the distribution of this firmware + * data in hexadecimal or equivalent format, provided this copyright + * notice is accompanying it. + */ + +/* + * Copyright (c) 2011-2013, Realtek Semiconductor Corporation + * + * Permission is hereby granted for the distribution of this firmware + * data in hexadecimal or equivalent format, provided this copyright + * notice is accompanying it. + */ + +#include "firmware_8125.h" + +const struct rtl8125_fw_pair rtl8125_mac_bps[256] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe012 }, { 0xf804, 0xe022 }, + { 0xf806, 0xe024 }, { 0xf808, 0xe029 }, { 0xf80a, 0xe02b }, + { 0xf80c, 0xe094 }, { 0xf80e, 0xe09d }, { 0xf810, 0xe09f }, + { 0xf812, 0xe0aa }, { 0xf814, 0xe0b5 }, { 0xf816, 0xe0c6 }, + { 0xf818, 0xe0cc }, { 0xf81a, 0xe0d1 }, { 0xf81c, 0xe0d6 }, + { 0xf81e, 0xe0d8 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 }, + { 0xf824, 0x0000 }, { 0xf826, 0xc60f }, { 0xf828, 0x73c4 }, + { 0xf82a, 0x49b3 }, { 0xf82c, 0xf106 }, { 0xf82e, 0x73c2 }, + { 0xf830, 0xc608 }, { 0xf832, 0xb406 }, { 0xf834, 0xc609 }, + { 0xf836, 0xff80 }, { 0xf838, 0xc605 }, { 0xf83a, 0xb406 }, + { 0xf83c, 0xc605 }, { 0xf83e, 0xff80 }, { 0xf840, 0x0544 }, + { 0xf842, 0x0568 }, { 0xf844, 0xe906 }, { 0xf846, 0xcde8 }, + { 0xf848, 0xc602 }, { 0xf84a, 0xbe00 }, { 0xf84c, 0x0000 }, + { 0xf84e, 0x48c1 }, { 0xf850, 0x48c2 }, { 0xf852, 0x9c46 }, + { 0xf854, 0xc402 }, { 0xf856, 0xbc00 }, { 0xf858, 0x0a12 }, + { 0xf85a, 0xc602 }, { 0xf85c, 0xbe00 }, { 0xf85e, 0x0eba }, + { 0xf860, 0x1501 }, { 0xf862, 0xf02a }, { 0xf864, 0x1500 }, + { 0xf866, 0xf15d }, { 0xf868, 0xc661 }, { 0xf86a, 0x75c8 }, + { 0xf86c, 0x49d5 }, { 0xf86e, 0xf00a }, { 0xf870, 0x49d6 }, + { 0xf872, 0xf008 }, { 0xf874, 0x49d7 }, { 0xf876, 0xf006 }, + { 0xf878, 0x49d8 }, { 0xf87a, 0xf004 }, { 0xf87c, 0x75d2 }, + { 0xf87e, 0x49d9 }, { 0xf880, 0xf150 }, { 0xf882, 0xc553 }, + { 0xf884, 0x77a0 }, { 0xf886, 0x75c8 }, { 0xf888, 0x4855 }, + { 0xf88a, 0x4856 }, { 0xf88c, 0x4857 }, { 0xf88e, 0x4858 }, + { 0xf890, 0x48da }, { 0xf892, 0x48db }, { 0xf894, 0x49fe }, + { 0xf896, 0xf002 }, { 0xf898, 0x485a }, { 0xf89a, 0x49ff }, + { 0xf89c, 0xf002 }, { 0xf89e, 0x485b }, { 0xf8a0, 0x9dc8 }, + { 0xf8a2, 0x75d2 }, { 0xf8a4, 0x4859 }, { 0xf8a6, 0x9dd2 }, + { 0xf8a8, 0xc643 }, { 0xf8aa, 0x75c0 }, { 0xf8ac, 0x49d4 }, + { 0xf8ae, 0xf033 }, { 0xf8b0, 0x49d0 }, { 0xf8b2, 0xf137 }, + { 0xf8b4, 0xe030 }, { 0xf8b6, 0xc63a }, { 0xf8b8, 0x75c8 }, + { 0xf8ba, 0x49d5 }, { 0xf8bc, 0xf00e }, { 0xf8be, 0x49d6 }, + { 0xf8c0, 0xf00c }, { 0xf8c2, 0x49d7 }, { 0xf8c4, 0xf00a }, + { 0xf8c6, 0x49d8 }, { 0xf8c8, 0xf008 }, { 0xf8ca, 0x75d2 }, + { 0xf8cc, 0x49d9 }, { 0xf8ce, 0xf005 }, { 0xf8d0, 0xc62e }, + { 0xf8d2, 0x75c0 }, { 0xf8d4, 0x49d7 }, { 0xf8d6, 0xf125 }, + { 0xf8d8, 0xc528 }, { 0xf8da, 0x77a0 }, { 0xf8dc, 0xc627 }, + { 0xf8de, 0x75c8 }, { 0xf8e0, 0x4855 }, { 0xf8e2, 0x4856 }, + { 0xf8e4, 0x4857 }, { 0xf8e6, 0x4858 }, { 0xf8e8, 0x48da }, + { 0xf8ea, 0x48db }, { 0xf8ec, 0x49fe }, { 0xf8ee, 0xf002 }, + { 0xf8f0, 0x485a }, { 0xf8f2, 0x49ff }, { 0xf8f4, 0xf002 }, + { 0xf8f6, 0x485b }, { 0xf8f8, 0x9dc8 }, { 0xf8fa, 0x75d2 }, + { 0xf8fc, 0x4859 }, { 0xf8fe, 0x9dd2 }, { 0xf900, 0xc616 }, + { 0xf902, 0x75c0 }, { 0xf904, 0x4857 }, { 0xf906, 0x9dc0 }, + { 0xf908, 0xc613 }, { 0xf90a, 0x75c0 }, { 0xf90c, 0x49da }, + { 0xf90e, 0xf003 }, { 0xf910, 0x49d0 }, { 0xf912, 0xf107 }, + { 0xf914, 0xc60b }, { 0xf916, 0xc50e }, { 0xf918, 0x48d9 }, + { 0xf91a, 0x9dc0 }, { 0xf91c, 0x4859 }, { 0xf91e, 0x9dc0 }, + { 0xf920, 0xc608 }, { 0xf922, 0xc702 }, { 0xf924, 0xbf00 }, + { 0xf926, 0x3ae0 }, { 0xf928, 0xe860 }, { 0xf92a, 0xb400 }, + { 0xf92c, 0xb5d4 }, { 0xf92e, 0xe908 }, { 0xf930, 0xe86c }, + { 0xf932, 0x1200 }, { 0xf934, 0xc409 }, { 0xf936, 0x6780 }, + { 0xf938, 0x48f1 }, { 0xf93a, 0x8f80 }, { 0xf93c, 0xc404 }, + { 0xf93e, 0xc602 }, { 0xf940, 0xbe00 }, { 0xf942, 0x10aa }, + { 0xf944, 0xc010 }, { 0xf946, 0xea7c }, { 0xf948, 0xc602 }, + { 0xf94a, 0xbe00 }, { 0xf94c, 0x0000 }, { 0xf94e, 0x740a }, + { 0xf950, 0x4846 }, { 0xf952, 0x4847 }, { 0xf954, 0x9c0a }, + { 0xf956, 0xc607 }, { 0xf958, 0x74c0 }, { 0xf95a, 0x48c6 }, + { 0xf95c, 0x9cc0 }, { 0xf95e, 0xc602 }, { 0xf960, 0xbe00 }, + { 0xf962, 0x13fe }, { 0xf964, 0xe054 }, { 0xf966, 0x72ca }, + { 0xf968, 0x4826 }, { 0xf96a, 0x4827 }, { 0xf96c, 0x9aca }, + { 0xf96e, 0xc607 }, { 0xf970, 0x72c0 }, { 0xf972, 0x48a6 }, + { 0xf974, 0x9ac0 }, { 0xf976, 0xc602 }, { 0xf978, 0xbe00 }, + { 0xf97a, 0x07dc }, { 0xf97c, 0xe054 }, { 0xf97e, 0xc60f }, + { 0xf980, 0x74c4 }, { 0xf982, 0x49cc }, { 0xf984, 0xf109 }, + { 0xf986, 0xc60c }, { 0xf988, 0x74ca }, { 0xf98a, 0x48c7 }, + { 0xf98c, 0x9cca }, { 0xf98e, 0xc609 }, { 0xf990, 0x74c0 }, + { 0xf992, 0x4846 }, { 0xf994, 0x9cc0 }, { 0xf996, 0xc602 }, + { 0xf998, 0xbe00 }, { 0xf99a, 0x2480 }, { 0xf99c, 0xe092 }, + { 0xf99e, 0xe0c0 }, { 0xf9a0, 0xe054 }, { 0xf9a2, 0x7420 }, + { 0xf9a4, 0x48c0 }, { 0xf9a6, 0x9c20 }, { 0xf9a8, 0x7444 }, + { 0xf9aa, 0xc602 }, { 0xf9ac, 0xbe00 }, { 0xf9ae, 0x12f8 }, + { 0xf9b0, 0x1bff }, { 0xf9b2, 0x46eb }, { 0xf9b4, 0x1bff }, + { 0xf9b6, 0xc102 }, { 0xf9b8, 0xb900 }, { 0xf9ba, 0x0d5a }, + { 0xf9bc, 0x1bff }, { 0xf9be, 0x46eb }, { 0xf9c0, 0x1bff }, + { 0xf9c2, 0xc102 }, { 0xf9c4, 0xb900 }, { 0xf9c6, 0x0e2a }, + { 0xf9c8, 0xc602 }, { 0xf9ca, 0xbe00 }, { 0xf9cc, 0x0000 }, + { 0xf9ce, 0xc602 }, { 0xf9d0, 0xbe00 }, { 0xf9d2, 0x0000 }, + { 0xf9d4, 0x0000 }, { 0xf9d6, 0x0000 }, { 0xf9d8, 0x0000 }, + { 0xf9da, 0x0000 }, { 0xf9dc, 0x0000 }, { 0xf9de, 0x0000 }, + { 0xf9e0, 0x0000 }, { 0xf9e2, 0x0000 }, { 0xf9e4, 0x0000 }, + { 0xf9e6, 0x0000 }, { 0xf9e8, 0x0000 }, { 0xf9ea, 0x0000 }, + { 0xf9ec, 0x0000 }, { 0xf9ee, 0x0000 }, { 0xf9f0, 0x0000 }, + { 0xf9f2, 0x0000 }, { 0xf9f4, 0x0000 }, { 0xf9f6, 0x0000 }, + { 0xf9f8, 0x0000 }, { 0xf9fa, 0x0000 }, { 0xf9fc, 0x0000 }, + { 0xf9fe, 0x0000 } +}; + +const struct rtl8125_fw_pair rtl8125b_mac_bps[138] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe01b }, { 0xf804, 0xe026 }, + { 0xf806, 0xe037 }, { 0xf808, 0xe03d }, { 0xf80a, 0xe057 }, + { 0xf80c, 0xe05b }, { 0xf80e, 0xe060 }, { 0xf810, 0xe062 }, + { 0xf812, 0xe064 }, { 0xf814, 0xe066 }, { 0xf816, 0xe068 }, + { 0xf818, 0xe06a }, { 0xf81a, 0xe06c }, { 0xf81c, 0xe06e }, + { 0xf81e, 0xe070 }, { 0xf820, 0x740a }, { 0xf822, 0x4846 }, + { 0xf824, 0x4847 }, { 0xf826, 0x9c0a }, { 0xf828, 0xc607 }, + { 0xf82a, 0x74c0 }, { 0xf82c, 0x48c6 }, { 0xf82e, 0x9cc0 }, + { 0xf830, 0xc602 }, { 0xf832, 0xbe00 }, { 0xf834, 0x13f0 }, + { 0xf836, 0xe054 }, { 0xf838, 0x72ca }, { 0xf83a, 0x4826 }, + { 0xf83c, 0x4827 }, { 0xf83e, 0x9aca }, { 0xf840, 0xc607 }, + { 0xf842, 0x72c0 }, { 0xf844, 0x48a6 }, { 0xf846, 0x9ac0 }, + { 0xf848, 0xc602 }, { 0xf84a, 0xbe00 }, { 0xf84c, 0x081c }, + { 0xf84e, 0xe054 }, { 0xf850, 0xc60f }, { 0xf852, 0x74c4 }, + { 0xf854, 0x49cc }, { 0xf856, 0xf109 }, { 0xf858, 0xc60c }, + { 0xf85a, 0x74ca }, { 0xf85c, 0x48c7 }, { 0xf85e, 0x9cca }, + { 0xf860, 0xc609 }, { 0xf862, 0x74c0 }, { 0xf864, 0x4846 }, + { 0xf866, 0x9cc0 }, { 0xf868, 0xc602 }, { 0xf86a, 0xbe00 }, + { 0xf86c, 0x2494 }, { 0xf86e, 0xe092 }, { 0xf870, 0xe0c0 }, + { 0xf872, 0xe054 }, { 0xf874, 0x7420 }, { 0xf876, 0x48c0 }, + { 0xf878, 0x9c20 }, { 0xf87a, 0x7444 }, { 0xf87c, 0xc602 }, + { 0xf87e, 0xbe00 }, { 0xf880, 0x12dc }, { 0xf882, 0x733a }, + { 0xf884, 0x21b5 }, { 0xf886, 0x25bc }, { 0xf888, 0x1304 }, + { 0xf88a, 0xf111 }, { 0xf88c, 0x1b12 }, { 0xf88e, 0x1d2a }, + { 0xf890, 0x3168 }, { 0xf892, 0x3ada }, { 0xf894, 0x31ab }, + { 0xf896, 0x1a00 }, { 0xf898, 0x9ac0 }, { 0xf89a, 0x1300 }, + { 0xf89c, 0xf1fb }, { 0xf89e, 0x7620 }, { 0xf8a0, 0x236e }, + { 0xf8a2, 0x276f }, { 0xf8a4, 0x1a3c }, { 0xf8a6, 0x22a1 }, + { 0xf8a8, 0x41b5 }, { 0xf8aa, 0x9ee2 }, { 0xf8ac, 0x76e4 }, + { 0xf8ae, 0x486f }, { 0xf8b0, 0x9ee4 }, { 0xf8b2, 0xc602 }, + { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x4a26 }, { 0xf8b8, 0x733a }, + { 0xf8ba, 0x49bb }, { 0xf8bc, 0xc602 }, { 0xf8be, 0xbe00 }, + { 0xf8c0, 0x47a2 }, { 0xf8c2, 0x48c1 }, { 0xf8c4, 0x48c2 }, + { 0xf8c6, 0x9c46 }, { 0xf8c8, 0xc402 }, { 0xf8ca, 0xbc00 }, + { 0xf8cc, 0x0a52 }, { 0xf8ce, 0xc602 }, { 0xf8d0, 0xbe00 }, + { 0xf8d2, 0x0000 }, { 0xf8d4, 0xc602 }, { 0xf8d6, 0xbe00 }, + { 0xf8d8, 0x0000 }, { 0xf8da, 0xc602 }, { 0xf8dc, 0xbe00 }, + { 0xf8de, 0x0000 }, { 0xf8e0, 0xc602 }, { 0xf8e2, 0xbe00 }, + { 0xf8e4, 0x0000 }, { 0xf8e6, 0xc602 }, { 0xf8e8, 0xbe00 }, + { 0xf8ea, 0x0000 }, { 0xf8ec, 0xc602 }, { 0xf8ee, 0xbe00 }, + { 0xf8f0, 0x0000 }, { 0xf8f2, 0xc602 }, { 0xf8f4, 0xbe00 }, + { 0xf8f6, 0x0000 }, { 0xf8f8, 0xc602 }, { 0xf8fa, 0xbe00 }, + { 0xf8fc, 0x0000 }, { 0xf8fe, 0xc602 }, { 0xf900, 0xbe00 }, + { 0xf902, 0x0000 }, { 0xfc26, 0x8000 }, { 0xfc28, 0x13e6 }, + { 0xfc2a, 0x0812 }, { 0xfc2c, 0x248c }, { 0xfc2e, 0x12da }, + { 0xfc30, 0x4a20 }, { 0xfc32, 0x47a0 }, { 0xfc48, 0x003f } +}; + +const struct rtl8125_fw_pair rtl8125d_2_mac_bps[66] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe014 }, { 0xf804, 0xe016 }, + { 0xf806, 0xe018 }, { 0xf808, 0xe01a }, { 0xf80a, 0xe01c }, + { 0xf80c, 0xe01e }, { 0xf80e, 0xe020 }, { 0xf810, 0xe022 }, + { 0xf812, 0xe024 }, { 0xf814, 0xe026 }, { 0xf816, 0xe028 }, + { 0xf818, 0xe02a }, { 0xf81a, 0xe02c }, { 0xf81c, 0xe02e }, + { 0xf81e, 0xe030 }, { 0xf820, 0xc104 }, { 0xf822, 0xc202 }, + { 0xf824, 0xba00 }, { 0xf826, 0x2384 }, { 0xf828, 0xd116 }, + { 0xf82a, 0xc602 }, { 0xf82c, 0xbe00 }, { 0xf82e, 0x0000 }, + { 0xf830, 0xc602 }, { 0xf832, 0xbe00 }, { 0xf834, 0x0000 }, + { 0xf836, 0xc602 }, { 0xf838, 0xbe00 }, { 0xf83a, 0x0000 }, + { 0xf83c, 0xc602 }, { 0xf83e, 0xbe00 }, { 0xf840, 0x0000 }, + { 0xf842, 0xc602 }, { 0xf844, 0xbe00 }, { 0xf846, 0x0000 }, + { 0xf848, 0xc602 }, { 0xf84a, 0xbe00 }, { 0xf84c, 0x0000 }, + { 0xf84e, 0xc602 }, { 0xf850, 0xbe00 }, { 0xf852, 0x0000 }, + { 0xf854, 0xc602 }, { 0xf856, 0xbe00 }, { 0xf858, 0x0000 }, + { 0xf85a, 0xc602 }, { 0xf85c, 0xbe00 }, { 0xf85e, 0x0000 }, + { 0xf860, 0xc602 }, { 0xf862, 0xbe00 }, { 0xf864, 0x0000 }, + { 0xf866, 0xc602 }, { 0xf868, 0xbe00 }, { 0xf86a, 0x0000 }, + { 0xf86c, 0xc602 }, { 0xf86e, 0xbe00 }, { 0xf870, 0x0000 }, + { 0xf872, 0xc602 }, { 0xf874, 0xbe00 }, { 0xf876, 0x0000 }, + { 0xf878, 0xc602 }, { 0xf87a, 0xbe00 }, { 0xf87c, 0x0000 }, + { 0xf87e, 0xc602 }, { 0xf880, 0xbe00 }, { 0xf882, 0x0000 } +}; + +const struct rtl8125_fw_pair mac_r25_mcu[550] = { + { 0xa436, 0xa016 }, { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x808b }, + { 0xa438, 0x1800 }, { 0xa438, 0x808f }, { 0xa438, 0x1800 }, + { 0xa438, 0x8093 }, { 0xa438, 0x1800 }, { 0xa438, 0x8097 }, + { 0xa438, 0x1800 }, { 0xa438, 0x809d }, { 0xa438, 0x1800 }, + { 0xa438, 0x80a1 }, { 0xa438, 0x1800 }, { 0xa438, 0x80aa }, + { 0xa438, 0xd718 }, { 0xa438, 0x607b }, { 0xa438, 0x40da }, + { 0xa438, 0xf00e }, { 0xa438, 0x42da }, { 0xa438, 0xf01e }, + { 0xa438, 0xd718 }, { 0xa438, 0x615b }, { 0xa438, 0x1000 }, + { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 }, + { 0xa438, 0x5f2e }, { 0xa438, 0xf01c }, { 0xa438, 0x1000 }, + { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 }, + { 0xa438, 0x5f2e }, { 0xa438, 0xf024 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 }, + { 0xa438, 0x5f2e }, { 0xa438, 0xf02c }, { 0xa438, 0x1000 }, + { 0xa438, 0x1456 }, { 0xa438, 0x1000 }, { 0xa438, 0x14a4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x14bc }, { 0xa438, 0xd718 }, + { 0xa438, 0x5f2e }, { 0xa438, 0xf034 }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac11 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa410 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x4779 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, + { 0xa438, 0xf034 }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac22 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa420 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd500 }, { 0xa438, 0x4559 }, { 0xa438, 0xd504 }, + { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, { 0xa438, 0xf023 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, + { 0xa438, 0xac44 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, + { 0xa438, 0xa440 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, + { 0xa438, 0x4339 }, { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, + { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1444 }, { 0xa438, 0xf012 }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac88 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa480 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x4119 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac0f }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1444 }, + { 0xa438, 0xf001 }, { 0xa438, 0x1000 }, { 0xa438, 0x1456 }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fac }, { 0xa438, 0xc48f }, + { 0xa438, 0x1000 }, { 0xa438, 0x141b }, { 0xa438, 0xd504 }, + { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x121a }, + { 0xa438, 0xd0b4 }, { 0xa438, 0xd1bb }, { 0xa438, 0x1800 }, + { 0xa438, 0x0898 }, { 0xa438, 0xd0b4 }, { 0xa438, 0xd1bb }, + { 0xa438, 0x1800 }, { 0xa438, 0x0a0e }, { 0xa438, 0xd064 }, + { 0xa438, 0xd18a }, { 0xa438, 0x1800 }, { 0xa438, 0x0b7e }, + { 0xa438, 0x401c }, { 0xa438, 0xd501 }, { 0xa438, 0xa804 }, + { 0xa438, 0x8804 }, { 0xa438, 0x1800 }, { 0xa438, 0x053b }, + { 0xa438, 0xd500 }, { 0xa438, 0xa301 }, { 0xa438, 0x1800 }, + { 0xa438, 0x0648 }, { 0xa438, 0xc520 }, { 0xa438, 0xa201 }, + { 0xa438, 0xd701 }, { 0xa438, 0x252d }, { 0xa438, 0x1646 }, + { 0xa438, 0xd708 }, { 0xa438, 0x4006 }, { 0xa438, 0x1800 }, + { 0xa438, 0x1646 }, { 0xa438, 0x1800 }, { 0xa438, 0x0308 }, + { 0xa436, 0xa026 }, { 0xa438, 0x0307 }, { 0xa436, 0xa024 }, + { 0xa438, 0x1645 }, { 0xa436, 0xa022 }, { 0xa438, 0x0647 }, + { 0xa436, 0xa020 }, { 0xa438, 0x053a }, { 0xa436, 0xa006 }, + { 0xa438, 0x0b7c }, { 0xa436, 0xa004 }, { 0xa438, 0x0a0c }, + { 0xa436, 0xa002 }, { 0xa438, 0x0896 }, { 0xa436, 0xa000 }, + { 0xa438, 0x11a1 }, { 0xa436, 0xa008 }, { 0xa438, 0xff00 }, + { 0xa436, 0xa016 }, { 0xa438, 0x0010 }, { 0xa436, 0xa012 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x8015 }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, + { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, + { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, + { 0xa438, 0xad02 }, { 0xa438, 0x1000 }, { 0xa438, 0x02d7 }, + { 0xa438, 0x1800 }, { 0xa438, 0x00ed }, { 0xa438, 0x0c0f }, + { 0xa438, 0x0509 }, { 0xa438, 0xc100 }, { 0xa438, 0x1800 }, + { 0xa438, 0x008f }, { 0xa436, 0xa08e }, { 0xa438, 0xffff }, + { 0xa436, 0xa08c }, { 0xa438, 0xffff }, { 0xa436, 0xa08a }, + { 0xa438, 0xffff }, { 0xa436, 0xa088 }, { 0xa438, 0xffff }, + { 0xa436, 0xa086 }, { 0xa438, 0xffff }, { 0xa436, 0xa084 }, + { 0xa438, 0xffff }, { 0xa436, 0xa082 }, { 0xa438, 0x008d }, + { 0xa436, 0xa080 }, { 0xa438, 0x00eb }, { 0xa436, 0xa090 }, + { 0xa438, 0x0103 }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, + { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8018 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8024 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8051 }, { 0xa438, 0x1800 }, { 0xa438, 0x8055 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8072 }, { 0xa438, 0x1800 }, + { 0xa438, 0x80dc }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0xfffd }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0xfffd }, + { 0xa438, 0x8301 }, { 0xa438, 0x800a }, { 0xa438, 0x8190 }, + { 0xa438, 0x82a0 }, { 0xa438, 0x8404 }, { 0xa438, 0xa70c }, + { 0xa438, 0x9402 }, { 0xa438, 0x890c }, { 0xa438, 0x8840 }, + { 0xa438, 0xa380 }, { 0xa438, 0x1800 }, { 0xa438, 0x066e }, + { 0xa438, 0xcb91 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, + { 0xa438, 0xd139 }, { 0xa438, 0xf002 }, { 0xa438, 0xd140 }, + { 0xa438, 0xd040 }, { 0xa438, 0xb404 }, { 0xa438, 0x0c0f }, + { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, { 0xa438, 0x07e0 }, + { 0xa438, 0xa610 }, { 0xa438, 0xa110 }, { 0xa438, 0xa2a0 }, + { 0xa438, 0xa404 }, { 0xa438, 0xd704 }, { 0xa438, 0x4085 }, + { 0xa438, 0xa180 }, { 0xa438, 0xa404 }, { 0xa438, 0x8280 }, + { 0xa438, 0xd704 }, { 0xa438, 0x405d }, { 0xa438, 0xa720 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0x1000 }, + { 0xa438, 0x07f0 }, { 0xa438, 0xd700 }, { 0xa438, 0x5f74 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0xd702 }, + { 0xa438, 0x7fb6 }, { 0xa438, 0x8190 }, { 0xa438, 0x82a0 }, + { 0xa438, 0x8404 }, { 0xa438, 0x8610 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0d01 }, { 0xa438, 0x1000 }, + { 0xa438, 0x07e0 }, { 0xa438, 0x1800 }, { 0xa438, 0x066e }, + { 0xa438, 0xd158 }, { 0xa438, 0xd04d }, { 0xa438, 0x1800 }, + { 0xa438, 0x03d4 }, { 0xa438, 0x94bc }, { 0xa438, 0x870c }, + { 0xa438, 0x8380 }, { 0xa438, 0xd10d }, { 0xa438, 0xd040 }, + { 0xa438, 0x1000 }, { 0xa438, 0x07c4 }, { 0xa438, 0xd700 }, + { 0xa438, 0x5fb4 }, { 0xa438, 0xa190 }, { 0xa438, 0xa00a }, + { 0xa438, 0xa280 }, { 0xa438, 0xa404 }, { 0xa438, 0xa220 }, + { 0xa438, 0xd130 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, + { 0xa438, 0x07c4 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, + { 0xa438, 0xbb80 }, { 0xa438, 0xd1c4 }, { 0xa438, 0xd074 }, + { 0xa438, 0xa301 }, { 0xa438, 0xd704 }, { 0xa438, 0x604b }, + { 0xa438, 0xa90c }, { 0xa438, 0x1800 }, { 0xa438, 0x0556 }, + { 0xa438, 0xcb92 }, { 0xa438, 0xd700 }, { 0xa438, 0x4063 }, + { 0xa438, 0xd116 }, { 0xa438, 0xf002 }, { 0xa438, 0xd119 }, + { 0xa438, 0xd040 }, { 0xa438, 0xd703 }, { 0xa438, 0x60a0 }, + { 0xa438, 0x6241 }, { 0xa438, 0x63e2 }, { 0xa438, 0x6583 }, + { 0xa438, 0xf054 }, { 0xa438, 0xd701 }, { 0xa438, 0x611e }, + { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0d10 }, { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, + { 0xa438, 0xf02f }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d50 }, + { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0xf02a }, + { 0xa438, 0xd701 }, { 0xa438, 0x611e }, { 0xa438, 0xd701 }, + { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d20 }, + { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, { 0xa438, 0xf021 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0d60 }, { 0xa438, 0x8010 }, + { 0xa438, 0xa740 }, { 0xa438, 0xf01c }, { 0xa438, 0xd701 }, + { 0xa438, 0x611e }, { 0xa438, 0xd701 }, { 0xa438, 0x40da }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0d30 }, { 0xa438, 0xa010 }, + { 0xa438, 0x8740 }, { 0xa438, 0xf013 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0d70 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, + { 0xa438, 0xf00e }, { 0xa438, 0xd701 }, { 0xa438, 0x611e }, + { 0xa438, 0xd701 }, { 0xa438, 0x40da }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0d40 }, { 0xa438, 0xa010 }, { 0xa438, 0x8740 }, + { 0xa438, 0xf005 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0d80 }, + { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, { 0xa438, 0x1000 }, + { 0xa438, 0x07e8 }, { 0xa438, 0xa610 }, { 0xa438, 0xd704 }, + { 0xa438, 0x405d }, { 0xa438, 0xa720 }, { 0xa438, 0xd700 }, + { 0xa438, 0x5ff4 }, { 0xa438, 0xa008 }, { 0xa438, 0xd704 }, + { 0xa438, 0x4046 }, { 0xa438, 0xa002 }, { 0xa438, 0x1000 }, + { 0xa438, 0x0743 }, { 0xa438, 0x1000 }, { 0xa438, 0x07fb }, + { 0xa438, 0xd703 }, { 0xa438, 0x7f6f }, { 0xa438, 0x7f4e }, + { 0xa438, 0x7f2d }, { 0xa438, 0x7f0c }, { 0xa438, 0x800a }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0d00 }, { 0xa438, 0x1000 }, + { 0xa438, 0x07e8 }, { 0xa438, 0x8010 }, { 0xa438, 0xa740 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0743 }, { 0xa438, 0xd702 }, + { 0xa438, 0x7fb5 }, { 0xa438, 0xd701 }, { 0xa438, 0x3ad4 }, + { 0xa438, 0x0556 }, { 0xa438, 0x8610 }, { 0xa438, 0x1800 }, + { 0xa438, 0x066e }, { 0xa438, 0xd1f5 }, { 0xa438, 0xd049 }, + { 0xa438, 0x1800 }, { 0xa438, 0x01ec }, { 0xa436, 0xa10e }, + { 0xa438, 0x01ea }, { 0xa436, 0xa10c }, { 0xa438, 0x06a9 }, + { 0xa436, 0xa10a }, { 0xa438, 0x078a }, { 0xa436, 0xa108 }, + { 0xa438, 0x03d2 }, { 0xa436, 0xa106 }, { 0xa438, 0x067f }, + { 0xa436, 0xa104 }, { 0xa438, 0x0665 }, { 0xa436, 0xa102 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa100 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa110 }, { 0xa438, 0x00fc }, { 0xa436, 0xb87c }, + { 0xa438, 0x8530 }, { 0xa436, 0xb87e }, { 0xa438, 0xaf85 }, + { 0xa438, 0x3caf }, { 0xa438, 0x8545 }, { 0xa438, 0xaf85 }, + { 0xa438, 0x45af }, { 0xa438, 0x8545 }, { 0xa438, 0xee82 }, + { 0xa438, 0xf900 }, { 0xa438, 0x0103 }, { 0xa438, 0xaf03 }, + { 0xa438, 0xb7f8 }, { 0xa438, 0xe0a6 }, { 0xa438, 0x00e1 }, + { 0xa438, 0xa601 }, { 0xa438, 0xef01 }, { 0xa438, 0x58f0 }, + { 0xa438, 0xa080 }, { 0xa438, 0x37a1 }, { 0xa438, 0x8402 }, + { 0xa438, 0xae16 }, { 0xa438, 0xa185 }, { 0xa438, 0x02ae }, + { 0xa438, 0x11a1 }, { 0xa438, 0x8702 }, { 0xa438, 0xae0c }, + { 0xa438, 0xa188 }, { 0xa438, 0x02ae }, { 0xa438, 0x07a1 }, + { 0xa438, 0x8902 }, { 0xa438, 0xae02 }, { 0xa438, 0xae1c }, + { 0xa438, 0xe0b4 }, { 0xa438, 0x62e1 }, { 0xa438, 0xb463 }, + { 0xa438, 0x6901 }, { 0xa438, 0xe4b4 }, { 0xa438, 0x62e5 }, + { 0xa438, 0xb463 }, { 0xa438, 0xe0b4 }, { 0xa438, 0x62e1 }, + { 0xa438, 0xb463 }, { 0xa438, 0x6901 }, { 0xa438, 0xe4b4 }, + { 0xa438, 0x62e5 }, { 0xa438, 0xb463 }, { 0xa438, 0xfc04 }, + { 0xa436, 0xb85e }, { 0xa438, 0x03b3 }, { 0xa436, 0xb860 }, + { 0xa438, 0xffff }, { 0xa436, 0xb862 }, { 0xa438, 0xffff }, + { 0xa436, 0xb864 }, { 0xa438, 0xffff }, { 0xa436, 0xb878 }, + { 0xa438, 0x0001 } +}; + +const struct rtl8125_fw_pair mac_r25b_mcu[1447] = { + { 0xa436, 0x8024 }, { 0xa438, 0x3701 }, { 0xa436, 0xb82e }, + { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, + { 0xa438, 0x803f }, { 0xa438, 0x1800 }, { 0xa438, 0x8045 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8067 }, { 0xa438, 0x1800 }, + { 0xa438, 0x806d }, { 0xa438, 0x1800 }, { 0xa438, 0x8071 }, + { 0xa438, 0x1800 }, { 0xa438, 0x80b1 }, { 0xa438, 0xd093 }, + { 0xa438, 0xd1c4 }, { 0xa438, 0x1000 }, { 0xa438, 0x135c }, + { 0xa438, 0xd704 }, { 0xa438, 0x5fbc }, { 0xa438, 0xd504 }, + { 0xa438, 0xc9f1 }, { 0xa438, 0x1800 }, { 0xa438, 0x0fc9 }, + { 0xa438, 0xbb50 }, { 0xa438, 0xd505 }, { 0xa438, 0xa202 }, + { 0xa438, 0xd504 }, { 0xa438, 0x8c0f }, { 0xa438, 0xd500 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1519 }, { 0xa438, 0x1000 }, + { 0xa438, 0x135c }, { 0xa438, 0xd75e }, { 0xa438, 0x5fae }, + { 0xa438, 0x9b50 }, { 0xa438, 0x1000 }, { 0xa438, 0x135c }, + { 0xa438, 0xd75e }, { 0xa438, 0x7fae }, { 0xa438, 0x1000 }, + { 0xa438, 0x135c }, { 0xa438, 0xd707 }, { 0xa438, 0x40a7 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4071 }, { 0xa438, 0x1800 }, + { 0xa438, 0x1557 }, { 0xa438, 0xd719 }, { 0xa438, 0x2f70 }, + { 0xa438, 0x803b }, { 0xa438, 0x2f73 }, { 0xa438, 0x156a }, + { 0xa438, 0x5e70 }, { 0xa438, 0x1800 }, { 0xa438, 0x155d }, + { 0xa438, 0xd505 }, { 0xa438, 0xa202 }, { 0xa438, 0xd500 }, + { 0xa438, 0xffed }, { 0xa438, 0xd709 }, { 0xa438, 0x4054 }, + { 0xa438, 0xa788 }, { 0xa438, 0xd70b }, { 0xa438, 0x1800 }, + { 0xa438, 0x172a }, { 0xa438, 0xc0c1 }, { 0xa438, 0xc0c0 }, + { 0xa438, 0xd05a }, { 0xa438, 0xd1ba }, { 0xa438, 0xd701 }, + { 0xa438, 0x2529 }, { 0xa438, 0x022a }, { 0xa438, 0xd0a7 }, + { 0xa438, 0xd1b9 }, { 0xa438, 0xa208 }, { 0xa438, 0x1000 }, + { 0xa438, 0x080e }, { 0xa438, 0xd701 }, { 0xa438, 0x408b }, + { 0xa438, 0x1000 }, { 0xa438, 0x0a65 }, { 0xa438, 0xf003 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0a6b }, { 0xa438, 0xd701 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0920 }, { 0xa438, 0x1000 }, + { 0xa438, 0x0915 }, { 0xa438, 0x1000 }, { 0xa438, 0x0909 }, + { 0xa438, 0x228f }, { 0xa438, 0x804e }, { 0xa438, 0x9801 }, + { 0xa438, 0xd71e }, { 0xa438, 0x5d61 }, { 0xa438, 0xd701 }, + { 0xa438, 0x1800 }, { 0xa438, 0x022a }, { 0xa438, 0x2005 }, + { 0xa438, 0x091a }, { 0xa438, 0x3bd9 }, { 0xa438, 0x0919 }, + { 0xa438, 0x1800 }, { 0xa438, 0x0916 }, { 0xa438, 0xd090 }, + { 0xa438, 0xd1c9 }, { 0xa438, 0x1800 }, { 0xa438, 0x1064 }, + { 0xa438, 0xd096 }, { 0xa438, 0xd1a9 }, { 0xa438, 0xd503 }, + { 0xa438, 0xa104 }, { 0xa438, 0x0c07 }, { 0xa438, 0x0902 }, + { 0xa438, 0xd500 }, { 0xa438, 0xbc10 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa201 }, { 0xa438, 0x8201 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0xc484 }, + { 0xa438, 0xd503 }, { 0xa438, 0xcc02 }, { 0xa438, 0xcd0d }, + { 0xa438, 0xaf01 }, { 0xa438, 0xd500 }, { 0xa438, 0xd703 }, + { 0xa438, 0x4371 }, { 0xa438, 0xbd08 }, { 0xa438, 0x1000 }, + { 0xa438, 0x135c }, { 0xa438, 0xd75e }, { 0xa438, 0x5fb3 }, + { 0xa438, 0xd503 }, { 0xa438, 0xd0f5 }, { 0xa438, 0xd1c6 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0e50 }, { 0xa438, 0xd704 }, + { 0xa438, 0x401c }, { 0xa438, 0xd0f5 }, { 0xa438, 0xd1c6 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0ea0 }, { 0xa438, 0x401c }, + { 0xa438, 0xd07b }, { 0xa438, 0xd1c5 }, { 0xa438, 0x8ef0 }, + { 0xa438, 0x401c }, { 0xa438, 0x9d08 }, { 0xa438, 0x1000 }, + { 0xa438, 0x135c }, { 0xa438, 0xd75e }, { 0xa438, 0x7fb3 }, + { 0xa438, 0x1000 }, { 0xa438, 0x135c }, { 0xa438, 0xd75e }, + { 0xa438, 0x5fad }, { 0xa438, 0x1000 }, { 0xa438, 0x14c5 }, + { 0xa438, 0xd703 }, { 0xa438, 0x3181 }, { 0xa438, 0x80af }, + { 0xa438, 0x60ad }, { 0xa438, 0x1000 }, { 0xa438, 0x135c }, + { 0xa438, 0xd703 }, { 0xa438, 0x5fba }, { 0xa438, 0x1800 }, + { 0xa438, 0x0cc7 }, { 0xa438, 0xa802 }, { 0xa438, 0xa301 }, + { 0xa438, 0xa801 }, { 0xa438, 0xc004 }, { 0xa438, 0xd710 }, + { 0xa438, 0x4000 }, { 0xa438, 0x1800 }, { 0xa438, 0x1e79 }, + { 0xa436, 0xa026 }, { 0xa438, 0x1e78 }, { 0xa436, 0xa024 }, + { 0xa438, 0x0c93 }, { 0xa436, 0xa022 }, { 0xa438, 0x1062 }, + { 0xa436, 0xa020 }, { 0xa438, 0x0915 }, { 0xa436, 0xa006 }, + { 0xa438, 0x020a }, { 0xa436, 0xa004 }, { 0xa438, 0x1726 }, + { 0xa436, 0xa002 }, { 0xa438, 0x1542 }, { 0xa436, 0xa000 }, + { 0xa438, 0x0fc7 }, { 0xa436, 0xa008 }, { 0xa438, 0xff00 }, + { 0xa436, 0xa016 }, { 0xa438, 0x0010 }, { 0xa436, 0xa012 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, { 0xa438, 0x801d }, + { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, + { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, + { 0xa438, 0x1800 }, { 0xa438, 0x802c }, { 0xa438, 0x1800 }, + { 0xa438, 0x802c }, { 0xa438, 0x1800 }, { 0xa438, 0x802c }, + { 0xa438, 0xd700 }, { 0xa438, 0x6090 }, { 0xa438, 0x60d1 }, + { 0xa438, 0xc95c }, { 0xa438, 0xf007 }, { 0xa438, 0x60b1 }, + { 0xa438, 0xc95a }, { 0xa438, 0xf004 }, { 0xa438, 0xc956 }, + { 0xa438, 0xf002 }, { 0xa438, 0xc94e }, { 0xa438, 0x1800 }, + { 0xa438, 0x00cd }, { 0xa438, 0xd700 }, { 0xa438, 0x6090 }, + { 0xa438, 0x60d1 }, { 0xa438, 0xc95c }, { 0xa438, 0xf007 }, + { 0xa438, 0x60b1 }, { 0xa438, 0xc95a }, { 0xa438, 0xf004 }, + { 0xa438, 0xc956 }, { 0xa438, 0xf002 }, { 0xa438, 0xc94e }, + { 0xa438, 0x1000 }, { 0xa438, 0x022a }, { 0xa438, 0x1800 }, + { 0xa438, 0x0132 }, { 0xa436, 0xa08e }, { 0xa438, 0xffff }, + { 0xa436, 0xa08c }, { 0xa438, 0xffff }, { 0xa436, 0xa08a }, + { 0xa438, 0xffff }, { 0xa436, 0xa088 }, { 0xa438, 0xffff }, + { 0xa436, 0xa086 }, { 0xa438, 0xffff }, { 0xa436, 0xa084 }, + { 0xa438, 0xffff }, { 0xa436, 0xa082 }, { 0xa438, 0x012f }, + { 0xa436, 0xa080 }, { 0xa438, 0x00cc }, { 0xa436, 0xa090 }, + { 0xa438, 0x0103 }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, + { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8020 }, { 0xa438, 0x1800 }, { 0xa438, 0x802a }, + { 0xa438, 0x1800 }, { 0xa438, 0x8035 }, { 0xa438, 0x1800 }, + { 0xa438, 0x803c }, { 0xa438, 0x1800 }, { 0xa438, 0x803c }, + { 0xa438, 0x1800 }, { 0xa438, 0x803c }, { 0xa438, 0x1800 }, + { 0xa438, 0x803c }, { 0xa438, 0xd107 }, { 0xa438, 0xd042 }, + { 0xa438, 0xa404 }, { 0xa438, 0x1000 }, { 0xa438, 0x09df }, + { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, { 0xa438, 0x8280 }, + { 0xa438, 0xd700 }, { 0xa438, 0x6065 }, { 0xa438, 0xd125 }, + { 0xa438, 0xf002 }, { 0xa438, 0xd12b }, { 0xa438, 0xd040 }, + { 0xa438, 0x1800 }, { 0xa438, 0x077f }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0c50 }, { 0xa438, 0xd104 }, { 0xa438, 0xd040 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0aa8 }, { 0xa438, 0xd700 }, + { 0xa438, 0x5fb4 }, { 0xa438, 0x1800 }, { 0xa438, 0x0a2e }, + { 0xa438, 0xcb9b }, { 0xa438, 0xd110 }, { 0xa438, 0xd040 }, + { 0xa438, 0x1000 }, { 0xa438, 0x0b7b }, { 0xa438, 0x1000 }, + { 0xa438, 0x09df }, { 0xa438, 0xd700 }, { 0xa438, 0x5fb4 }, + { 0xa438, 0x1800 }, { 0xa438, 0x081b }, { 0xa438, 0x1000 }, + { 0xa438, 0x09df }, { 0xa438, 0xd704 }, { 0xa438, 0x7fb8 }, + { 0xa438, 0xa718 }, { 0xa438, 0x1800 }, { 0xa438, 0x074e }, + { 0xa436, 0xa10e }, { 0xa438, 0xffff }, { 0xa436, 0xa10c }, + { 0xa438, 0xffff }, { 0xa436, 0xa10a }, { 0xa438, 0xffff }, + { 0xa436, 0xa108 }, { 0xa438, 0xffff }, { 0xa436, 0xa106 }, + { 0xa438, 0x074d }, { 0xa436, 0xa104 }, { 0xa438, 0x0818 }, + { 0xa436, 0xa102 }, { 0xa438, 0x0a2c }, { 0xa436, 0xa100 }, + { 0xa438, 0x077e }, { 0xa436, 0xa110 }, { 0xa438, 0x000f }, + { 0xa436, 0xb87c }, { 0xa438, 0x8625 }, { 0xa436, 0xb87e }, + { 0xa438, 0xaf86 }, { 0xa438, 0x3daf }, { 0xa438, 0x8689 }, + { 0xa438, 0xaf88 }, { 0xa438, 0x69af }, { 0xa438, 0x8887 }, + { 0xa438, 0xaf88 }, { 0xa438, 0x9caf }, { 0xa438, 0x88be }, + { 0xa438, 0xaf88 }, { 0xa438, 0xbeaf }, { 0xa438, 0x88be }, + { 0xa438, 0xbf86 }, { 0xa438, 0x49d7 }, { 0xa438, 0x0040 }, + { 0xa438, 0x0277 }, { 0xa438, 0x7daf }, { 0xa438, 0x2727 }, + { 0xa438, 0x0000 }, { 0xa438, 0x7205 }, { 0xa438, 0x0000 }, + { 0xa438, 0x7208 }, { 0xa438, 0x0000 }, { 0xa438, 0x71f3 }, + { 0xa438, 0x0000 }, { 0xa438, 0x71f6 }, { 0xa438, 0x0000 }, + { 0xa438, 0x7229 }, { 0xa438, 0x0000 }, { 0xa438, 0x722c }, + { 0xa438, 0x0000 }, { 0xa438, 0x7217 }, { 0xa438, 0x0000 }, + { 0xa438, 0x721a }, { 0xa438, 0x0000 }, { 0xa438, 0x721d }, + { 0xa438, 0x0000 }, { 0xa438, 0x7211 }, { 0xa438, 0x0000 }, + { 0xa438, 0x7220 }, { 0xa438, 0x0000 }, { 0xa438, 0x7214 }, + { 0xa438, 0x0000 }, { 0xa438, 0x722f }, { 0xa438, 0x0000 }, + { 0xa438, 0x7223 }, { 0xa438, 0x0000 }, { 0xa438, 0x7232 }, + { 0xa438, 0x0000 }, { 0xa438, 0x7226 }, { 0xa438, 0xf8f9 }, + { 0xa438, 0xfae0 }, { 0xa438, 0x85b3 }, { 0xa438, 0x3802 }, + { 0xa438, 0xad27 }, { 0xa438, 0x02ae }, { 0xa438, 0x03af }, + { 0xa438, 0x8830 }, { 0xa438, 0x1f66 }, { 0xa438, 0xef65 }, + { 0xa438, 0xbfc2 }, { 0xa438, 0x1f1a }, { 0xa438, 0x96f7 }, + { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, { 0xa438, 0x00da }, + { 0xa438, 0xf605 }, { 0xa438, 0xbfc2 }, { 0xa438, 0x2f1a }, + { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, + { 0xa438, 0x00db }, { 0xa438, 0xf605 }, { 0xa438, 0xef02 }, + { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, + { 0xa438, 0x4202 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef02 }, + { 0xa438, 0x1b03 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, + { 0xa438, 0xbf88 }, { 0xa438, 0x4502 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xef02 }, { 0xa438, 0x1a03 }, { 0xa438, 0x1f11 }, + { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x4802 }, + { 0xa438, 0x6e7d }, { 0xa438, 0xbfc2 }, { 0xa438, 0x3f1a }, + { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, { 0xa438, 0xffd2 }, + { 0xa438, 0x00da }, { 0xa438, 0xf605 }, { 0xa438, 0xbfc2 }, + { 0xa438, 0x4f1a }, { 0xa438, 0x96f7 }, { 0xa438, 0x05ee }, + { 0xa438, 0xffd2 }, { 0xa438, 0x00db }, { 0xa438, 0xf605 }, + { 0xa438, 0xef02 }, { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, + { 0xa438, 0xbf88 }, { 0xa438, 0x4b02 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xef02 }, { 0xa438, 0x1b03 }, { 0xa438, 0x1f11 }, + { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, { 0xa438, 0x4e02 }, + { 0xa438, 0x6e7d }, { 0xa438, 0xef02 }, { 0xa438, 0x1a03 }, + { 0xa438, 0x1f11 }, { 0xa438, 0x0d42 }, { 0xa438, 0xbf88 }, + { 0xa438, 0x5102 }, { 0xa438, 0x6e7d }, { 0xa438, 0xef56 }, + { 0xa438, 0xd020 }, { 0xa438, 0x1f11 }, { 0xa438, 0xbf88 }, + { 0xa438, 0x5402 }, { 0xa438, 0x6e7d }, { 0xa438, 0xbf88 }, + { 0xa438, 0x5702 }, { 0xa438, 0x6e7d }, { 0xa438, 0xbf88 }, + { 0xa438, 0x5a02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe185 }, + { 0xa438, 0xa0ef }, { 0xa438, 0x0348 }, { 0xa438, 0x0a28 }, + { 0xa438, 0x05ef }, { 0xa438, 0x201b }, { 0xa438, 0x01ad }, + { 0xa438, 0x2735 }, { 0xa438, 0x1f44 }, { 0xa438, 0xe085 }, + { 0xa438, 0x88e1 }, { 0xa438, 0x8589 }, { 0xa438, 0xbf88 }, + { 0xa438, 0x5d02 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, + { 0xa438, 0x8ee1 }, { 0xa438, 0x858f }, { 0xa438, 0xbf88 }, + { 0xa438, 0x6002 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, + { 0xa438, 0x94e1 }, { 0xa438, 0x8595 }, { 0xa438, 0xbf88 }, + { 0xa438, 0x6302 }, { 0xa438, 0x6e7d }, { 0xa438, 0xe085 }, + { 0xa438, 0x9ae1 }, { 0xa438, 0x859b }, { 0xa438, 0xbf88 }, + { 0xa438, 0x6602 }, { 0xa438, 0x6e7d }, { 0xa438, 0xaf88 }, + { 0xa438, 0x3cbf }, { 0xa438, 0x883f }, { 0xa438, 0x026e }, + { 0xa438, 0x9cad }, { 0xa438, 0x2835 }, { 0xa438, 0x1f44 }, + { 0xa438, 0xe08f }, { 0xa438, 0xf8e1 }, { 0xa438, 0x8ff9 }, + { 0xa438, 0xbf88 }, { 0xa438, 0x5d02 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xe08f }, { 0xa438, 0xfae1 }, { 0xa438, 0x8ffb }, + { 0xa438, 0xbf88 }, { 0xa438, 0x6002 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xe08f }, { 0xa438, 0xfce1 }, { 0xa438, 0x8ffd }, + { 0xa438, 0xbf88 }, { 0xa438, 0x6302 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xe08f }, { 0xa438, 0xfee1 }, { 0xa438, 0x8fff }, + { 0xa438, 0xbf88 }, { 0xa438, 0x6602 }, { 0xa438, 0x6e7d }, + { 0xa438, 0xaf88 }, { 0xa438, 0x3ce1 }, { 0xa438, 0x85a1 }, + { 0xa438, 0x1b21 }, { 0xa438, 0xad37 }, { 0xa438, 0x341f }, + { 0xa438, 0x44e0 }, { 0xa438, 0x858a }, { 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}, + { 0xa438, 0xa200 }, { 0xa438, 0x04ef }, { 0xa438, 0x32ae }, + { 0xa438, 0x02d3 }, { 0xa438, 0x010c }, { 0xa438, 0x31bf }, + { 0xa438, 0x8fed }, { 0xa438, 0x1a93 }, { 0xa438, 0xd819 }, + { 0xa438, 0xd91b }, { 0xa438, 0x46ab }, { 0xa438, 0x0e19 }, + { 0xa438, 0xd819 }, { 0xa438, 0xd91b }, { 0xa438, 0x46aa }, + { 0xa438, 0x0612 }, { 0xa438, 0xa205 }, { 0xa438, 0xc0ae }, + { 0xa438, 0x0cbf }, { 0xa438, 0x5712 }, { 0xa438, 0x0258 }, + { 0xa438, 0xb1bf }, { 0xa438, 0x5712 }, { 0xa438, 0x0258 }, + { 0xa438, 0xa8fe }, { 0xa438, 0xef96 }, { 0xa438, 0xfffe }, + { 0xa438, 0xfdfc }, { 0xa438, 0x04f8 }, { 0xa438, 0xfbef }, + { 0xa438, 0x79a2 }, { 0xa438, 0x0005 }, { 0xa438, 0xbf89 }, + { 0xa438, 0x1fae }, { 0xa438, 0x1ba2 }, { 0xa438, 0x0105 }, + { 0xa438, 0xbf89 }, { 0xa438, 0x22ae }, { 0xa438, 0x13a2 }, + { 0xa438, 0x0205 }, { 0xa438, 0xbf89 }, { 0xa438, 0x25ae }, + { 0xa438, 0x0ba2 }, { 0xa438, 0x0305 }, { 0xa438, 0xbf89 }, + { 0xa438, 0x28ae }, { 0xa438, 0x03bf }, { 0xa438, 0x892b }, + { 0xa438, 0x0252 }, { 0xa438, 0xc8ef }, { 0xa438, 0x64ef }, + { 0xa438, 0x97ff }, { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, + { 0xa438, 0xfaef }, { 0xa438, 0x69fa }, { 0xa438, 0xe080 }, + { 0xa438, 0x15ad }, { 0xa438, 0x2628 }, { 0xa438, 0xe081 }, + { 0xa438, 0xabe1 }, { 0xa438, 0x81ac }, { 0xa438, 0xef64 }, + { 0xa438, 0xbf57 }, { 0xa438, 0x1802 }, { 0xa438, 0x52c8 }, + { 0xa438, 0x1b46 }, { 0xa438, 0xaa0a }, { 0xa438, 0xbf57 }, + { 0xa438, 0x1b02 }, { 0xa438, 0x52c8 }, { 0xa438, 0x1b46 }, + { 0xa438, 0xab0c }, { 0xa438, 0xbf57 }, { 0xa438, 0x1502 }, + { 0xa438, 0x58b1 }, { 0xa438, 0xbf57 }, { 0xa438, 0x1502 }, + { 0xa438, 0x58a8 }, { 0xa438, 0xfeef }, { 0xa438, 0x96fe }, + { 0xa438, 0xfdfc }, { 0xa438, 0x04f8 }, { 0xa438, 0xf9ef }, + { 0xa438, 0x59f9 }, { 0xa438, 0xe080 }, { 0xa438, 0x15ad }, + { 0xa438, 0x2622 }, { 0xa438, 0xbf53 }, { 0xa438, 0x2202 }, + { 0xa438, 0x52c8 }, { 0xa438, 0x3972 }, { 0xa438, 0x9e10 }, + { 0xa438, 0xe083 }, { 0xa438, 0xc9ac }, { 0xa438, 0x2605 }, + { 0xa438, 0x0288 }, { 0xa438, 0x2cae }, { 0xa438, 0x0d02 }, + { 0xa438, 0x8870 }, { 0xa438, 0xae08 }, { 0xa438, 0xe283 }, + { 0xa438, 0xc9f6 }, { 0xa438, 0x36e6 }, { 0xa438, 0x83c9 }, + { 0xa438, 0xfdef }, { 0xa438, 0x95fd }, { 0xa438, 0xfc04 }, + { 0xa438, 0xf8f9 }, { 0xa438, 0xfafb }, { 0xa438, 0xef79 }, + { 0xa438, 0xfbbf }, { 0xa438, 0x5718 }, { 0xa438, 0x0252 }, + { 0xa438, 0xc8ef }, { 0xa438, 0x64e2 }, { 0xa438, 0x8fe5 }, + { 0xa438, 0xe38f }, { 0xa438, 0xe61b }, { 0xa438, 0x659e }, + { 0xa438, 0x10e4 }, { 0xa438, 0x8fe5 }, { 0xa438, 0xe58f }, + { 0xa438, 0xe6e2 }, { 0xa438, 0x83c9 }, { 0xa438, 0xf636 }, + { 0xa438, 0xe683 }, { 0xa438, 0xc9ae }, { 0xa438, 0x13e2 }, + { 0xa438, 0x83c9 }, { 0xa438, 0xf736 }, { 0xa438, 0xe683 }, + { 0xa438, 0xc902 }, { 0xa438, 0x5820 }, { 0xa438, 0xef57 }, + { 0xa438, 0xe68f }, { 0xa438, 0xe7e7 }, { 0xa438, 0x8fe8 }, + { 0xa438, 0xffef }, { 0xa438, 0x97ff }, { 0xa438, 0xfefd }, + { 0xa438, 0xfc04 }, { 0xa438, 0xf8f9 }, { 0xa438, 0xfafb }, + { 0xa438, 0xef79 }, { 0xa438, 0xfbe2 }, { 0xa438, 0x8fe7 }, + { 0xa438, 0xe38f }, { 0xa438, 0xe8ef }, { 0xa438, 0x65e2 }, + { 0xa438, 0x81b8 }, { 0xa438, 0xe381 }, { 0xa438, 0xb9ef }, + { 0xa438, 0x7502 }, { 0xa438, 0x583b }, { 0xa438, 0xac50 }, + { 0xa438, 0x1abf }, { 0xa438, 0x5718 }, { 0xa438, 0x0252 }, + { 0xa438, 0xc8ef }, { 0xa438, 0x64e2 }, { 0xa438, 0x8fe5 }, + { 0xa438, 0xe38f }, { 0xa438, 0xe61b }, { 0xa438, 0x659e }, + { 0xa438, 0x1ce4 }, { 0xa438, 0x8fe5 }, { 0xa438, 0xe58f }, + { 0xa438, 0xe6ae }, { 0xa438, 0x0cbf }, { 0xa438, 0x5715 }, + { 0xa438, 0x0258 }, { 0xa438, 0xb1bf }, { 0xa438, 0x5715 }, + { 0xa438, 0x0258 }, { 0xa438, 0xa8e2 }, { 0xa438, 0x83c9 }, + { 0xa438, 0xf636 }, { 0xa438, 0xe683 }, { 0xa438, 0xc9ff }, + { 0xa438, 0xef97 }, { 0xa438, 0xfffe }, { 0xa438, 0xfdfc }, + { 0xa438, 0x04f8 }, { 0xa438, 0xf9fa }, { 0xa438, 0xef69 }, + { 0xa438, 0xe080 }, { 0xa438, 0x15ad }, { 0xa438, 0x264b }, + { 0xa438, 0xbf53 }, { 0xa438, 0xca02 }, { 0xa438, 0x52c8 }, + { 0xa438, 0xad28 }, { 0xa438, 0x42bf }, { 0xa438, 0x8931 }, + { 0xa438, 0x0252 }, { 0xa438, 0xc8ef }, { 0xa438, 0x54bf }, + { 0xa438, 0x576c }, { 0xa438, 0x0252 }, { 0xa438, 0xc8a1 }, + { 0xa438, 0x001b }, { 0xa438, 0xbf53 }, { 0xa438, 0x4c02 }, + { 0xa438, 0x52c8 }, { 0xa438, 0xac29 }, { 0xa438, 0x0dac }, + { 0xa438, 0x2805 }, { 0xa438, 0xa302 }, { 0xa438, 0x16ae }, + { 0xa438, 0x20a3 }, { 0xa438, 0x0311 }, { 0xa438, 0xae1b }, + { 0xa438, 0xa304 }, { 0xa438, 0x0cae }, { 0xa438, 0x16a3 }, + { 0xa438, 0x0802 }, { 0xa438, 0xae11 }, { 0xa438, 0xa309 }, + { 0xa438, 0x02ae }, { 0xa438, 0x0cbf }, { 0xa438, 0x5715 }, + { 0xa438, 0x0258 }, { 0xa438, 0xb1bf }, { 0xa438, 0x5715 }, + { 0xa438, 0x0258 }, { 0xa438, 0xa8ef }, { 0xa438, 0x96fe }, + { 0xa438, 0xfdfc }, { 0xa438, 0x04f0 }, { 0xa438, 0xa300 }, + { 0xa438, 0xf0a3 }, { 0xa438, 0x02f0 }, { 0xa438, 0xa304 }, + { 0xa438, 0xf0a3 }, { 0xa438, 0x06f0 }, { 0xa438, 0xa308 }, + { 0xa438, 0xf0a2 }, { 0xa438, 0x8074 }, { 0xa438, 0xa600 }, + { 0xa438, 0xac4f }, { 0xa438, 0x02ae }, { 0xa438, 0x0bef }, + { 0xa438, 0x46f6 }, { 0xa438, 0x273c }, { 0xa438, 0x1000 }, + { 0xa438, 0xab1b }, { 0xa438, 0xae16 }, { 0xa438, 0xe081 }, + { 0xa438, 0xabe1 }, { 0xa438, 0x81ac }, { 0xa438, 0x1b46 }, + { 0xa438, 0xab0c }, { 0xa438, 0xac32 }, { 0xa438, 0x04ef }, + { 0xa438, 0x32ae }, { 0xa438, 0x02d3 }, { 0xa438, 0x04af }, + { 0xa438, 0x486c }, { 0xa438, 0xaf48 }, { 0xa438, 0x82af }, + { 0xa438, 0x4888 }, { 0xa438, 0xe081 }, { 0xa438, 0x9be1 }, + { 0xa438, 0x819c }, { 0xa438, 0xe28f }, { 0xa438, 0xe3ad }, + { 0xa438, 0x3009 }, { 0xa438, 0x1f55 }, { 0xa438, 0xe38f }, + { 0xa438, 0xe20c }, { 0xa438, 0x581a }, { 0xa438, 0x45e4 }, + { 0xa438, 0x83a6 }, { 0xa438, 0xe583 }, { 0xa438, 0xa7af }, + { 0xa438, 0x2a75 }, { 0xa438, 0xe08f }, { 0xa438, 0xe3ad }, + { 0xa438, 0x201c }, { 0xa438, 0x1f44 }, { 0xa438, 0xe18f }, + { 0xa438, 0xe10c }, { 0xa438, 0x44ef }, { 0xa438, 0x64e0 }, + { 0xa438, 0x8232 }, { 0xa438, 0xe182 }, { 0xa438, 0x331b }, + { 0xa438, 0x649f }, { 0xa438, 0x091f }, { 0xa438, 0x44e1 }, + { 0xa438, 0x8fe2 }, { 0xa438, 0x0c48 }, { 0xa438, 0x1b54 }, + { 0xa438, 0xe683 }, { 0xa438, 0xa6e7 }, { 0xa438, 0x83a7 }, + { 0xa438, 0xaf2b }, { 0xa438, 0xd900 }, { 0xa436, 0xb818 }, + { 0xa438, 0x043d }, { 0xa436, 0xb81a }, { 0xa438, 0x06a3 }, + { 0xa436, 0xb81c }, { 0xa438, 0x476d }, { 0xa436, 0xb81e }, + { 0xa438, 0x4852 }, { 0xa436, 0xb850 }, { 0xa438, 0x2a69 }, + { 0xa436, 0xb852 }, { 0xa438, 0x2bd3 }, { 0xa436, 0xb878 }, + { 0xa438, 0xffff }, { 0xa436, 0xb884 }, { 0xa438, 0xffff }, + { 0xa436, 0xb832 }, { 0xa438, 0x003f }, { 0xb844, 0xffff }, + { 0xa436, 0x8fe9 }, { 0xa438, 0x0000 }, { 0xa436, 0x8feb }, + { 0xa438, 0x02fe }, { 0xa436, 0x8fed }, { 0xa438, 0x0019 }, + { 0xa436, 0x8fef }, { 0xa438, 0x0bdb }, { 0xa436, 0x8ff1 }, + { 0xa438, 0x0ca4 }, { 0xa436, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa436, 0xb82e }, { 0xa438, 0x0000 }, { 0xa436, 0x8024 }, + { 0xa438, 0x0000 }, { 0xa436, 0x801e }, { 0xa438, 0x0024 }, + { 0xb820, 0x0000 } +}; + +const struct rtl8125_fw_pair mac_r25d_1_mcu[3241] = { + { 0xa436, 0x8023 }, { 0xa438, 0x3800 }, { 0xa436, 0xb82e }, + { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8018 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8021 }, { 0xa438, 0x1800 }, { 0xa438, 0x8029 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8031 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8035 }, { 0xa438, 0x1800 }, { 0xa438, 0x819c }, + { 0xa438, 0x1800 }, { 0xa438, 0x81e9 }, { 0xa438, 0xd711 }, + { 0xa438, 0x6081 }, { 0xa438, 0x8904 }, { 0xa438, 0x1800 }, + { 0xa438, 0x2021 }, { 0xa438, 0xa904 }, { 0xa438, 0x1800 }, + { 0xa438, 0x2021 }, { 0xa438, 0xd75f }, { 0xa438, 0x4083 }, + { 0xa438, 0xd503 }, { 0xa438, 0xa908 }, { 0xa438, 0x87f0 }, + { 0xa438, 0x1000 }, { 0xa438, 0x17e0 }, { 0xa438, 0x1800 }, + { 0xa438, 0x13c3 }, { 0xa438, 0xd707 }, { 0xa438, 0x2005 }, + { 0xa438, 0x8027 }, { 0xa438, 0xd75e }, { 0xa438, 0x1800 }, + { 0xa438, 0x1434 }, { 0xa438, 0x1800 }, { 0xa438, 0x14a5 }, + { 0xa438, 0xc504 }, { 0xa438, 0xce20 }, { 0xa438, 0xcf01 }, + { 0xa438, 0xd70a }, { 0xa438, 0x4005 }, { 0xa438, 0xcf02 }, + { 0xa438, 0x1800 }, { 0xa438, 0x1c50 }, { 0xa438, 0xa980 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1800 }, { 0xa438, 0x14f3 }, + { 0xa438, 0xd75e }, { 0xa438, 0x67b1 }, { 0xa438, 0xd504 }, + { 0xa438, 0xd71e }, { 0xa438, 0x65bb }, { 0xa438, 0x63da }, + { 0xa438, 0x61f9 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0c10 }, + { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0808 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0470 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0430 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0410 }, { 0xa438, 0xf02a }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0c20 }, { 0xa438, 0xd505 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0804 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0470 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0430 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0420 }, { 0xa438, 0xf01c }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0c40 }, { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, + { 0xa438, 0x0802 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0470 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0450 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0440 }, + { 0xa438, 0xf00e }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0c80 }, + { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0801 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x04b0 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0490 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0480 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0xc48e }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, + { 0xa438, 0x5faf }, { 0xa438, 0xd504 }, { 0xa438, 0x8e01 }, + { 0xa438, 0x8c0f }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x17e0 }, { 0xa438, 0xd504 }, { 0xa438, 0xd718 }, + { 0xa438, 0x4074 }, { 0xa438, 0x6195 }, { 0xa438, 0xf005 }, + { 0xa438, 0x60f5 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0d00 }, + { 0xa438, 0xf009 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0d01 }, + { 0xa438, 0xf006 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0d02 }, + { 0xa438, 0xf003 }, { 0xa438, 0x0c03 }, { 0xa438, 0x0d03 }, + { 0xa438, 0xd500 }, { 0xa438, 0xd706 }, { 0xa438, 0x2529 }, + { 0xa438, 0x809c }, { 0xa438, 0xd718 }, { 0xa438, 0x607b }, + { 0xa438, 0x40da }, { 0xa438, 0xf00f }, { 0xa438, 0x431a }, + { 0xa438, 0xf021 }, { 0xa438, 0xd718 }, { 0xa438, 0x617b }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1ad1 }, { 0xa438, 0xd718 }, { 0xa438, 0x608e }, + { 0xa438, 0xd73e }, { 0xa438, 0x5f34 }, { 0xa438, 0xf020 }, + { 0xa438, 0xf053 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1ad1 }, { 0xa438, 0xd718 }, + { 0xa438, 0x608e }, { 0xa438, 0xd73e }, { 0xa438, 0x5f34 }, + { 0xa438, 0xf023 }, { 0xa438, 0xf067 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0x1000 }, { 0xa438, 0x1ad1 }, + { 0xa438, 0xd718 }, { 0xa438, 0x608e }, { 0xa438, 0xd73e }, + { 0xa438, 0x5f34 }, { 0xa438, 0xf026 }, { 0xa438, 0xf07b }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1ad1 }, { 0xa438, 0xd718 }, { 0xa438, 0x608e }, + { 0xa438, 0xd73e }, { 0xa438, 0x5f34 }, { 0xa438, 0xf029 }, + { 0xa438, 0xf08f }, { 0xa438, 0x1000 }, { 0xa438, 0x8173 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0xd73e }, + { 0xa438, 0x7fb4 }, { 0xa438, 0x1000 }, { 0xa438, 0x8188 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, + { 0xa438, 0x5fae }, { 0xa438, 0xf028 }, { 0xa438, 0x1000 }, + { 0xa438, 0x8173 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, + { 0xa438, 0xd73e }, { 0xa438, 0x7fb4 }, { 0xa438, 0x1000 }, + { 0xa438, 0x8188 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fae }, { 0xa438, 0xf039 }, + { 0xa438, 0x1000 }, { 0xa438, 0x8173 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd73e }, { 0xa438, 0x7fb4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x8188 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fae }, + { 0xa438, 0xf04a }, { 0xa438, 0x1000 }, { 0xa438, 0x8173 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0xd73e }, + { 0xa438, 0x7fb4 }, { 0xa438, 0x1000 }, { 0xa438, 0x8188 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, + { 0xa438, 0x5fae }, { 0xa438, 0xf05b }, { 0xa438, 0xd719 }, + { 0xa438, 0x4119 }, { 0xa438, 0xd504 }, { 0xa438, 0xac01 }, + { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a2f }, { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac11 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa410 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, + { 0xa438, 0xd505 }, { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, + { 0xa438, 0xa80f }, { 0xa438, 0xf05d }, { 0xa438, 0x4b98 }, + { 0xa438, 0xa808 }, { 0xa438, 0xf05a }, { 0xa438, 0xd719 }, + { 0xa438, 0x4119 }, { 0xa438, 0xd504 }, { 0xa438, 0xac02 }, + { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a2f }, { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac22 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa420 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, + { 0xa438, 0xd505 }, { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, + { 0xa438, 0xa80f }, { 0xa438, 0xf03f }, { 0xa438, 0x47d8 }, + { 0xa438, 0xa804 }, { 0xa438, 0xf03c }, { 0xa438, 0xd719 }, + { 0xa438, 0x4119 }, { 0xa438, 0xd504 }, { 0xa438, 0xac04 }, + { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a2f }, { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac44 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa440 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, + { 0xa438, 0xd505 }, { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, + { 0xa438, 0xa80f }, { 0xa438, 0xf021 }, { 0xa438, 0x4418 }, + { 0xa438, 0xa802 }, { 0xa438, 0xf01e }, { 0xa438, 0xd719 }, + { 0xa438, 0x4119 }, { 0xa438, 0xd504 }, { 0xa438, 0xac08 }, + { 0xa438, 0xae01 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a2f }, { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, + { 0xa438, 0x4118 }, { 0xa438, 0xd504 }, { 0xa438, 0xac88 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa480 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a41 }, { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, + { 0xa438, 0xd505 }, { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, + { 0xa438, 0xa80f }, { 0xa438, 0xf003 }, { 0xa438, 0x4058 }, + { 0xa438, 0xa801 }, { 0xa438, 0x1800 }, { 0xa438, 0x16ed }, + { 0xa438, 0xd73e }, { 0xa438, 0xd505 }, { 0xa438, 0x3088 }, + { 0xa438, 0x817a }, { 0xa438, 0x6193 }, { 0xa438, 0x6132 }, + { 0xa438, 0x60d1 }, { 0xa438, 0x3298 }, { 0xa438, 0x8185 }, + { 0xa438, 0xf00a }, { 0xa438, 0xa808 }, { 0xa438, 0xf008 }, + { 0xa438, 0xa804 }, { 0xa438, 0xf006 }, { 0xa438, 0xa802 }, + { 0xa438, 0xf004 }, { 0xa438, 0xa801 }, { 0xa438, 0xf002 }, + { 0xa438, 0xa80f }, { 0xa438, 0xd500 }, { 0xa438, 0x0800 }, + { 0xa438, 0xd505 }, { 0xa438, 0xd75e }, { 0xa438, 0x6211 }, + { 0xa438, 0xd71e }, { 0xa438, 0x619b }, { 0xa438, 0x611a }, + { 0xa438, 0x6099 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0808 }, + { 0xa438, 0xf009 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0804 }, + { 0xa438, 0xf006 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0802 }, + { 0xa438, 0xf003 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0801 }, + { 0xa438, 0xd500 }, { 0xa438, 0x0800 }, { 0xa438, 0xd500 }, + { 0xa438, 0xc48d }, { 0xa438, 0xd504 }, { 0xa438, 0x8d03 }, + { 0xa438, 0xd701 }, { 0xa438, 0x4045 }, { 0xa438, 0xad02 }, + { 0xa438, 0xd504 }, { 0xa438, 0xd706 }, { 0xa438, 0x2529 }, + { 0xa438, 0x81ad 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0xc294 }, + { 0xb890, 0xa328 }, { 0xb88e, 0xc295 }, { 0xb890, 0xa332 }, + { 0xb88e, 0xc296 }, { 0xb890, 0xd72b }, { 0xb88e, 0xc297 }, + { 0xb890, 0xd735 }, { 0xb88e, 0xc298 }, { 0xb890, 0x8a2e }, + { 0xb88e, 0xc299 }, { 0xb890, 0x8a38 }, { 0xb88e, 0xc29a }, + { 0xb890, 0xbe32 }, { 0xb88e, 0xc29b }, { 0xb890, 0xbe3c }, + { 0xb88e, 0xc29c }, { 0xb890, 0x7436 }, { 0xb88e, 0xc29d }, + { 0xb890, 0x7440 }, { 0xb88e, 0xc29e }, { 0xb890, 0xad3b }, + { 0xb88e, 0xc29f }, { 0xb890, 0xad45 }, { 0xb88e, 0xc2a0 }, + { 0xb890, 0x6640 }, { 0xb88e, 0xc2a1 }, { 0xb890, 0x664a }, + { 0xb88e, 0xc2a2 }, { 0xb890, 0xa646 }, { 0xb88e, 0xc2a3 }, + { 0xb890, 0xa650 }, { 0xb88e, 0xc2a4 }, { 0xb890, 0x624c }, + { 0xb88e, 0xc2a5 }, { 0xb890, 0x6256 }, { 0xb88e, 0xc2a6 }, + { 0xb890, 0xa453 }, { 0xb88e, 0xc2a7 }, { 0xb890, 0xa45d }, + { 0xb88e, 0xc2a8 }, { 0xb890, 0x665a }, { 0xb88e, 0xc2a9 }, + { 0xb890, 0x6664 }, { 0xb88e, 0xc2aa }, { 0xb890, 0xac62 }, + { 0xb88e, 0xc2ab }, { 0xb890, 0xac6c }, { 0xb88e, 0xc2ac }, + { 0xb890, 0x746a }, { 0xb88e, 0xc2ad }, { 0xb890, 0x7474 }, + { 0xb88e, 0xc2ae }, { 0xb890, 0xbcfa }, { 0xb88e, 0xc2af }, + { 0xb890, 0xbcfd }, { 0xb88e, 0xc2b0 }, { 0xb890, 0x79ff }, + { 0xb88e, 0xc2b1 }, { 0xb890, 0x7901 }, { 0xb88e, 0xc2b2 }, + { 0xb890, 0xf703 }, { 0xb88e, 0xc2b3 }, { 0xb890, 0xf706 }, + { 0xb88e, 0xc2b4 }, { 0xb890, 0x7408 }, { 0xb88e, 0xc2b5 }, + { 0xb890, 0x740a }, { 0xb88e, 0xc2b6 }, { 0xb890, 0xf10c }, + { 0xb88e, 0xc2b7 }, { 0xb890, 0xf10f }, { 0xb88e, 0xc2b8 }, + { 0xb890, 0x6f10 }, { 0xb88e, 0xc2b9 }, { 0xb890, 0x6f13 }, + { 0xb88e, 0xc2ba }, { 0xb890, 0xec15 }, { 0xb88e, 0xc2bb }, + { 0xb890, 0xec18 }, { 0xb88e, 0xc2bc }, { 0xb890, 0x6a1a }, + { 0xb88e, 0xc2bd }, { 0xb890, 0x6a1c }, { 0xb88e, 0xc2be }, + { 0xb890, 0xe71e }, { 0xb88e, 0xc2bf }, { 0xb890, 0xe721 }, + { 0xb88e, 0xc2c0 }, { 0xb890, 0x6424 }, { 0xb88e, 0xc2c1 }, + { 0xb890, 0x6425 }, { 0xb88e, 0xc2c2 }, { 0xb890, 0xe228 }, + { 0xb88e, 0xc2c3 }, { 0xb890, 0xe22a }, { 0xb88e, 0xc2c4 }, + { 0xb890, 0x5f2b }, { 0xb88e, 0xc2c5 }, { 0xb890, 0x5f2e }, + { 0xb88e, 0xc2c6 }, { 0xb890, 0xdc31 }, { 0xb88e, 0xc2c7 }, + { 0xb890, 0xdc33 }, { 0xb88e, 0xc2c8 }, { 0xb890, 0x2035 }, + { 0xb88e, 0xc2c9 }, { 0xb890, 0x2036 }, { 0xb88e, 0xc2ca }, + { 0xb890, 0x9f3a }, { 0xb88e, 0xc2cb }, { 0xb890, 0x9f3a }, + { 0xb88e, 0xc2cc }, { 0xb890, 0x4430 }, { 0xa436, 0xacca }, + { 0xa438, 0x0104 }, { 0xa436, 0xaccc }, { 0xa438, 0x8000 }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0fff }, { 0xa436, 0xacce }, { 0xa438, 0xfd47 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0fff }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xe56f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01c0 }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xed97 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01c8 }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xf5bf }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01d0 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb07 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb0f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01d8 }, { 0xa436, 0xacce }, { 0xa438, 0xa087 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, { 0xa436, 0xacce }, + { 0xa438, 0xa00f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, + { 0xa436, 0xacce }, { 0xa438, 0xa807 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0100 }, { 0xa436, 0xacce }, { 0xa438, 0xa88f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, { 0xa436, 0xacce }, + { 0xa438, 0xb027 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, + { 0xa436, 0xacce }, { 0xa438, 0xb02f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0128 }, { 0xa436, 0xacce }, { 0xa438, 0xb847 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, { 0xa436, 0xacce }, + { 0xa438, 0xb84f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb17 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb1f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xa017 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0110 }, + { 0xa436, 0xacce }, { 0xa438, 0xa01f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0118 }, { 0xa436, 0xacce }, { 0xa438, 0xa837 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, { 0xa436, 0xacce }, + { 0xa438, 0xa83f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0138 }, + { 0xa436, 0xacce }, { 0xa438, 0xb097 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0190 }, { 0xa436, 0xacce }, { 0xa438, 0xb05f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, { 0xa436, 0xacce }, + { 0xa438, 0xb857 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0150 }, + { 0xa436, 0xacce }, { 0xa438, 0xb89f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0198 }, { 0xa436, 0xacce }, { 0xa438, 0xfb27 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb2f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x8087 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0180 }, { 0xa436, 0xacce }, { 0xa438, 0x800f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, { 0xa436, 0xacce }, + { 0xa438, 0x8807 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0100 }, + { 0xa436, 0xacce }, { 0xa438, 0x888f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0188 }, { 0xa436, 0xacce }, { 0xa438, 0x9027 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, { 0xa436, 0xacce }, + { 0xa438, 0x902f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0128 }, + { 0xa436, 0xacce }, { 0xa438, 0x9847 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0140 }, { 0xa436, 0xacce }, { 0xa438, 0x984f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, { 0xa436, 0xacce }, + { 0xa438, 0xa0a7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01a0 }, + { 0xa436, 0xacce }, { 0xa438, 0xa8af }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, { 0xa438, 0xa067 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, { 0xa436, 0xacce }, + { 0xa438, 0xa86f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb37 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb3f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0x8017 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0110 }, + { 0xa436, 0xacce }, { 0xa438, 0x801f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0118 }, { 0xa436, 0xacce }, { 0xa438, 0x8837 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, { 0xa436, 0xacce }, + { 0xa438, 0x883f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0138 }, + { 0xa436, 0xacce }, { 0xa438, 0x9097 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0190 }, { 0xa436, 0xacce }, { 0xa438, 0x905f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, { 0xa436, 0xacce }, + { 0xa438, 0x9857 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0150 }, + { 0xa436, 0xacce }, { 0xa438, 0x989f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0198 }, { 0xa436, 0xacce }, { 0xa438, 0xb0b7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, + { 0xa438, 0xb8bf }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, + { 0xa436, 0xacce }, { 0xa438, 0xb077 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0171 }, { 0xa436, 0xacce }, { 0xa438, 0xb87f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb47 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb4f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x6087 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, { 0xa436, 0xacce }, + { 0xa438, 0x600f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, + { 0xa436, 0xacce }, { 0xa438, 0x6807 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0100 }, { 0xa436, 0xacce }, { 0xa438, 0x688f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, { 0xa436, 0xacce }, + { 0xa438, 0x7027 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, + { 0xa436, 0xacce }, { 0xa438, 0x702f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0128 }, { 0xa436, 0xacce }, { 0xa438, 0x7847 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, { 0xa436, 0xacce }, + { 0xa438, 0x784f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, + { 0xa436, 0xacce }, { 0xa438, 0x80a7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, { 0xa438, 0x88af }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, + { 0xa438, 0x8067 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, + { 0xa436, 0xacce }, { 0xa438, 0x886f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0169 }, { 0xa436, 0xacce }, { 0xa438, 0xfb57 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb5f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x6017 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0110 }, { 0xa436, 0xacce }, { 0xa438, 0x601f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, { 0xa436, 0xacce }, + { 0xa438, 0x6837 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, + { 0xa436, 0xacce }, { 0xa438, 0x683f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0138 }, { 0xa436, 0xacce }, { 0xa438, 0x7097 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, { 0xa436, 0xacce }, + { 0xa438, 0x705f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, + { 0xa436, 0xacce }, { 0xa438, 0x7857 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0150 }, { 0xa436, 0xacce }, { 0xa438, 0x789f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, { 0xa436, 0xacce }, + { 0xa438, 0x90b7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, + { 0xa436, 0xacce }, { 0xa438, 0x98bf }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, { 0xa438, 0x9077 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, { 0xa436, 0xacce }, + { 0xa438, 0x987f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb67 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb6f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0x4087 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, + { 0xa436, 0xacce }, { 0xa438, 0x400f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0108 }, { 0xa436, 0xacce }, { 0xa438, 0x4807 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0100 }, { 0xa436, 0xacce }, + { 0xa438, 0x488f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, + { 0xa436, 0xacce }, { 0xa438, 0x5027 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0120 }, { 0xa436, 0xacce }, { 0xa438, 0x502f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0128 }, { 0xa436, 0xacce }, + { 0xa438, 0x5847 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, + { 0xa436, 0xacce }, { 0xa438, 0x584f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0148 }, { 0xa436, 0xacce }, { 0xa438, 0x60a7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, + { 0xa438, 0x68af }, { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, + { 0xa436, 0xacce }, { 0xa438, 0x6067 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0161 }, { 0xa436, 0xacce }, { 0xa438, 0x686f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb77 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb7f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x4017 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0110 }, { 0xa436, 0xacce }, + { 0xa438, 0x401f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, + { 0xa436, 0xacce }, { 0xa438, 0x4837 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0130 }, { 0xa436, 0xacce }, { 0xa438, 0x483f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0138 }, { 0xa436, 0xacce }, + { 0xa438, 0x5097 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, + { 0xa436, 0xacce }, { 0xa438, 0x505f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0158 }, { 0xa436, 0xacce }, { 0xa438, 0x5857 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0150 }, { 0xa436, 0xacce }, + { 0xa438, 0x589f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, + { 0xa436, 0xacce }, { 0xa438, 0x70b7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, { 0xa438, 0x78bf }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, + { 0xa438, 0x7077 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, + { 0xa436, 0xacce }, { 0xa438, 0x787f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0179 }, { 0xa436, 0xacce }, { 0xa438, 0xfb87 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb8f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x40a7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, { 0xa438, 0x48af }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, + { 0xa438, 0x4067 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, + { 0xa436, 0xacce }, { 0xa438, 0x486f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0169 }, { 0xa436, 0xacce }, { 0xa438, 0xfb97 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb9f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x50b7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, { 0xa438, 0x58bf }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, + { 0xa438, 0x5077 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, + { 0xa436, 0xacce }, { 0xa438, 0x587f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0179 }, { 0xa436, 0xacce }, { 0xa438, 0xfba7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfbaf }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x2067 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0161 }, { 0xa436, 0xacce }, { 0xa438, 0x286f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, { 0xa436, 0xacce }, + { 0xa438, 0xfbb7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfbbf }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x3077 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, { 0xa436, 0xacce }, + { 0xa438, 0x387f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, + { 0xa436, 0xacce }, { 0xa438, 0xfff9 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x17ff }, { 0xa436, 0xacce }, { 0xa438, 0xfff9 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x17ff }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x0fff }, + { 0xa436, 0xacce }, { 0xa438, 0xfff8 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0fff }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb47 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb4f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x6087 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, { 0xa436, 0xacce }, + { 0xa438, 0x600f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, + { 0xa436, 0xacce }, { 0xa438, 0x6807 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0100 }, { 0xa436, 0xacce }, { 0xa438, 0x688f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, { 0xa436, 0xacce }, + { 0xa438, 0x7027 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, + { 0xa436, 0xacce }, { 0xa438, 0x702f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0128 }, { 0xa436, 0xacce }, { 0xa438, 0x7847 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, { 0xa436, 0xacce }, + { 0xa438, 0x784f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, + { 0xa436, 0xacce }, { 0xa438, 0x80a7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, { 0xa438, 0x88af }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, + { 0xa438, 0x8067 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, + { 0xa436, 0xacce }, { 0xa438, 0x886f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0169 }, { 0xa436, 0xacce }, { 0xa438, 0xfb57 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb5f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x6017 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0110 }, { 0xa436, 0xacce }, { 0xa438, 0x601f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, { 0xa436, 0xacce }, + { 0xa438, 0x6837 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, + { 0xa436, 0xacce }, { 0xa438, 0x683f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0138 }, { 0xa436, 0xacce }, { 0xa438, 0x7097 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, { 0xa436, 0xacce }, + { 0xa438, 0x705f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, + { 0xa436, 0xacce }, { 0xa438, 0x7857 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0150 }, { 0xa436, 0xacce }, { 0xa438, 0x789f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, { 0xa436, 0xacce }, + { 0xa438, 0x90b7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, + { 0xa436, 0xacce }, { 0xa438, 0x98bf }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, { 0xa438, 0x9077 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x1171 }, { 0xa436, 0xacce }, + { 0xa438, 0x987f }, { 0xa436, 0xacd0 }, { 0xa438, 0x1179 }, + { 0xa436, 0xacca }, { 0xa438, 0x0004 }, { 0xa436, 0xacc6 }, + { 0xa438, 0x0008 }, { 0xa436, 0xacc8 }, { 0xa438, 0xc000 }, + { 0xa436, 0xacc6 }, { 0xa438, 0x0015 }, { 0xa436, 0xacc8 }, + { 0xa438, 0xc043 }, { 0xa436, 0xacc8 }, { 0xa438, 0x0000 }, + { 0xb820, 0x0000 } +}; + +const struct rtl8125_fw_pair mac_r25d_2_mcu[1818] = { + { 0xa436, 0x8023 }, { 0xa438, 0x3801 }, { 0xa436, 0xb82e }, + { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, + { 0xa438, 0x1800 }, { 0xa438, 0x808e }, { 0xa438, 0x1800 }, + { 0xa438, 0x80d6 }, { 0xa438, 0x1800 }, { 0xa438, 0x81e2 }, + { 0xa438, 0x1800 }, { 0xa438, 0x81e2 }, { 0xa438, 0x1800 }, + { 0xa438, 0x81e2 }, { 0xa438, 0x1800 }, { 0xa438, 0x81e2 }, + { 0xa438, 0x1800 }, { 0xa438, 0x81e2 }, { 0xa438, 0xd500 }, + { 0xa438, 0xc48d }, { 0xa438, 0xd504 }, { 0xa438, 0x8d03 }, + { 0xa438, 0xd701 }, { 0xa438, 0x4045 }, { 0xa438, 0xad02 }, + { 0xa438, 0xd504 }, { 0xa438, 0xd706 }, { 0xa438, 0x2529 }, + { 0xa438, 0x8021 }, { 0xa438, 0xd718 }, { 0xa438, 0x607b }, + { 0xa438, 0x40da }, { 0xa438, 0xf019 }, { 0xa438, 0x459a }, + { 0xa438, 0xf03f }, { 0xa438, 0xd718 }, { 0xa438, 0x62bb }, + { 0xa438, 0xbb01 }, { 0xa438, 0xd75e }, { 0xa438, 0x6231 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0c10 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, { 0xa438, 0x6147 }, + { 0xa438, 0x8480 }, { 0xa438, 0x8440 }, { 0xa438, 0x8420 }, + { 0xa438, 0xa410 }, { 0xa438, 0xce00 }, { 0xa438, 0xd505 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0808 }, { 0xa438, 0xf002 }, + { 0xa438, 0xa4f0 }, { 0xa438, 0xf03c }, { 0xa438, 0xbb02 }, + { 0xa438, 0xd75e }, { 0xa438, 0x6231 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0c20 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, + { 0xa438, 0xd70c }, { 0xa438, 0x6147 }, { 0xa438, 0x8480 }, + { 0xa438, 0x8440 }, { 0xa438, 0xa420 }, { 0xa438, 0x8410 }, + { 0xa438, 0xce00 }, { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, + { 0xa438, 0x0804 }, { 0xa438, 0xf002 }, { 0xa438, 0xa4f0 }, + { 0xa438, 0xf028 }, { 0xa438, 0xbb04 }, { 0xa438, 0xd75e }, + { 0xa438, 0x6231 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0c40 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, + { 0xa438, 0x6147 }, { 0xa438, 0x8480 }, { 0xa438, 0xa440 }, + { 0xa438, 0x8420 }, { 0xa438, 0x8410 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0802 }, + { 0xa438, 0xf002 }, { 0xa438, 0xa4f0 }, { 0xa438, 0xf014 }, + { 0xa438, 0xbb08 }, { 0xa438, 0xd75e }, { 0xa438, 0x6231 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0c80 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, { 0xa438, 0x6147 }, + { 0xa438, 0xa480 }, { 0xa438, 0x8440 }, { 0xa438, 0x8420 }, + { 0xa438, 0x8410 }, { 0xa438, 0xce00 }, { 0xa438, 0xd505 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0801 }, { 0xa438, 0xf002 }, + { 0xa438, 0xa4f0 }, { 0xa438, 0xce00 }, { 0xa438, 0xd500 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, { 0xa438, 0x1000 }, + { 0xa438, 0x1829 }, { 0xa438, 0xd73e }, { 0xa438, 0x6074 }, + { 0xa438, 0xd718 }, { 0xa438, 0x5f2d }, { 0xa438, 0x1000 }, + { 0xa438, 0x81b7 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0x1000 }, { 0xa438, 0x1829 }, { 0xa438, 0xd73e }, + { 0xa438, 0x7f74 }, { 0xa438, 0x1000 }, { 0xa438, 0x81ce }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, { 0xa438, 0x1000 }, + { 0xa438, 0x1829 }, { 0xa438, 0xd718 }, { 0xa438, 0x5f6d }, + { 0xa438, 0x1800 }, { 0xa438, 0x1660 }, { 0xa438, 0xd75e }, + { 0xa438, 0x68b1 }, { 0xa438, 0xd504 }, { 0xa438, 0xd71e }, + { 0xa438, 0x667b }, { 0xa438, 0x645a }, { 0xa438, 0x6239 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0c10 }, { 0xa438, 0xd505 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0808 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, { 0xa438, 0x60c7 }, + { 0xa438, 0x8480 }, { 0xa438, 0x8440 }, { 0xa438, 0x8420 }, + { 0xa438, 0xa410 }, { 0xa438, 0xf032 }, { 0xa438, 0xa4f0 }, + { 0xa438, 0xf030 }, { 0xa438, 0x0cf0 }, { 0xa438, 0x0c20 }, + { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, { 0xa438, 0x0804 }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, + { 0xa438, 0x60c7 }, { 0xa438, 0x8480 }, { 0xa438, 0x8440 }, + { 0xa438, 0xa420 }, { 0xa438, 0x8410 }, { 0xa438, 0xf022 }, + { 0xa438, 0xa4f0 }, { 0xa438, 0xf020 }, { 0xa438, 0x0cf0 }, + { 0xa438, 0x0c40 }, { 0xa438, 0xd505 }, { 0xa438, 0x0c0f }, + { 0xa438, 0x0802 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, + { 0xa438, 0xd70c }, { 0xa438, 0x60c7 }, { 0xa438, 0x8480 }, + { 0xa438, 0xa440 }, { 0xa438, 0x8420 }, { 0xa438, 0x8410 }, + { 0xa438, 0xf012 }, { 0xa438, 0xa4f0 }, { 0xa438, 0xf010 }, + { 0xa438, 0x0cf0 }, { 0xa438, 0x0c80 }, { 0xa438, 0xd505 }, + { 0xa438, 0x0c0f }, { 0xa438, 0x0801 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xd70c }, { 0xa438, 0x60c7 }, + { 0xa438, 0xa480 }, { 0xa438, 0x8440 }, { 0xa438, 0x8420 }, + { 0xa438, 0x8410 }, { 0xa438, 0xf002 }, { 0xa438, 0xa4f0 }, + { 0xa438, 0x1800 }, { 0xa438, 0x168c }, { 0xa438, 0xd500 }, + { 0xa438, 0xd706 }, { 0xa438, 0x2529 }, { 0xa438, 0x80e0 }, + { 0xa438, 0xd718 }, { 0xa438, 0x607b }, { 0xa438, 0x40da }, + { 0xa438, 0xf00f }, { 0xa438, 0x431a }, { 0xa438, 0xf021 }, + { 0xa438, 0xd718 }, { 0xa438, 0x617b }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0x1000 }, { 0xa438, 0x1b1a }, + { 0xa438, 0xd718 }, { 0xa438, 0x608e }, { 0xa438, 0xd73e }, + { 0xa438, 0x5f34 }, { 0xa438, 0xf020 }, { 0xa438, 0xf053 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, { 0xa438, 0x1000 }, + { 0xa438, 0x1b1a }, { 0xa438, 0xd718 }, { 0xa438, 0x608e }, + { 0xa438, 0xd73e }, { 0xa438, 0x5f34 }, { 0xa438, 0xf023 }, + { 0xa438, 0xf067 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0x1000 }, { 0xa438, 0x1b1a }, { 0xa438, 0xd718 }, + { 0xa438, 0x608e }, { 0xa438, 0xd73e }, { 0xa438, 0x5f34 }, + { 0xa438, 0xf026 }, { 0xa438, 0xf07b }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0x1000 }, { 0xa438, 0x1b1a }, + { 0xa438, 0xd718 }, { 0xa438, 0x608e }, { 0xa438, 0xd73e }, + { 0xa438, 0x5f34 }, { 0xa438, 0xf029 }, { 0xa438, 0xf08f }, + { 0xa438, 0x1000 }, { 0xa438, 0x81b7 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0xd73e }, { 0xa438, 0x7fb4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x81ce }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0xd718 }, { 0xa438, 0x5fae }, + { 0xa438, 0xf028 }, { 0xa438, 0x1000 }, { 0xa438, 0x81b7 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, { 0xa438, 0xd73e }, + { 0xa438, 0x7fb4 }, { 0xa438, 0x1000 }, { 0xa438, 0x81ce }, + { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, { 0xa438, 0xd718 }, + { 0xa438, 0x5fae }, { 0xa438, 0xf039 }, { 0xa438, 0x1000 }, + { 0xa438, 0x81b7 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd73e }, { 0xa438, 0x7fb4 }, { 0xa438, 0x1000 }, + { 0xa438, 0x81ce }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fae }, { 0xa438, 0xf04a }, + { 0xa438, 0x1000 }, { 0xa438, 0x81b7 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0xd73e }, { 0xa438, 0x7fb4 }, + { 0xa438, 0x1000 }, { 0xa438, 0x81ce }, { 0xa438, 0x1000 }, + { 0xa438, 0x1a8a }, { 0xa438, 0xd718 }, { 0xa438, 0x5fae }, + { 0xa438, 0xf05b }, { 0xa438, 0xd719 }, { 0xa438, 0x4119 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac01 }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a78 }, + { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac11 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa410 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, { 0xa438, 0xd505 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, { 0xa438, 0xa80f }, + { 0xa438, 0xf05d }, { 0xa438, 0x4b98 }, { 0xa438, 0xa808 }, + { 0xa438, 0xf05a }, { 0xa438, 0xd719 }, { 0xa438, 0x4119 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac02 }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a78 }, + { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac22 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa420 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, { 0xa438, 0xd505 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, { 0xa438, 0xa80f }, + { 0xa438, 0xf03f }, { 0xa438, 0x47d8 }, { 0xa438, 0xa804 }, + { 0xa438, 0xf03c }, { 0xa438, 0xd719 }, { 0xa438, 0x4119 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac04 }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a78 }, + { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac44 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa440 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, { 0xa438, 0xd505 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, { 0xa438, 0xa80f }, + { 0xa438, 0xf021 }, { 0xa438, 0x4418 }, { 0xa438, 0xa802 }, + { 0xa438, 0xf01e }, { 0xa438, 0xd719 }, { 0xa438, 0x4119 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac08 }, { 0xa438, 0xae01 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a78 }, + { 0xa438, 0xf00a }, { 0xa438, 0xd719 }, { 0xa438, 0x4118 }, + { 0xa438, 0xd504 }, { 0xa438, 0xac88 }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa480 }, { 0xa438, 0xce00 }, + { 0xa438, 0xd500 }, { 0xa438, 0x1000 }, { 0xa438, 0x1a8a }, + { 0xa438, 0xd718 }, { 0xa438, 0x5fb0 }, { 0xa438, 0xd505 }, + { 0xa438, 0xd719 }, { 0xa438, 0x4079 }, { 0xa438, 0xa80f }, + { 0xa438, 0xf003 }, { 0xa438, 0x4058 }, { 0xa438, 0xa801 }, + { 0xa438, 0x1800 }, { 0xa438, 0x1736 }, { 0xa438, 0xd73e }, + { 0xa438, 0xd505 }, { 0xa438, 0x3088 }, { 0xa438, 0x81c0 }, + { 0xa438, 0x61d3 }, { 0xa438, 0x6172 }, { 0xa438, 0x6111 }, + { 0xa438, 0x60b0 }, { 0xa438, 0xf00d }, { 0xa438, 0x3298 }, + { 0xa438, 0x81cb }, { 0xa438, 0xf00a }, { 0xa438, 0xa808 }, + { 0xa438, 0xf008 }, { 0xa438, 0xa804 }, { 0xa438, 0xf006 }, + { 0xa438, 0xa802 }, { 0xa438, 0xf004 }, { 0xa438, 0xa801 }, + { 0xa438, 0xf002 }, { 0xa438, 0xa80f }, { 0xa438, 0xd500 }, + { 0xa438, 0x0800 }, { 0xa438, 0xd505 }, { 0xa438, 0xd75e }, + { 0xa438, 0x6211 }, { 0xa438, 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0x1502 }, + { 0xa438, 0x8570 }, { 0xa438, 0x9503 }, { 0xa438, 0xd704 }, + { 0xa438, 0x60f3 }, { 0xa438, 0xd71f }, { 0xa438, 0x60ee }, + { 0xa438, 0xd700 }, { 0xa438, 0x5bbe }, { 0xa438, 0x1800 }, + { 0xa438, 0x0e71 }, { 0xa438, 0x1800 }, { 0xa438, 0x0e7c }, + { 0xa438, 0x1800 }, { 0xa438, 0x0e7e }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0xaf80 }, { 0xa438, 0x9503 }, + { 0xa438, 0xcd62 }, { 0xa438, 0x1800 }, { 0xa438, 0x0bd2 }, + { 0xa438, 0x800a }, { 0xa438, 0x8530 }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0x8d10 }, { 0xa438, 0x9503 }, + { 0xa438, 0xd700 }, { 0xa438, 0x6050 }, { 0xa438, 0xaa20 }, + { 0xa438, 0x8306 }, { 0xa438, 0x1800 }, { 0xa438, 0x0cb6 }, + { 0xa438, 0xd105 }, { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, + { 0xa438, 0x0d8f }, { 0xa438, 0xd700 }, { 0xa438, 0x5fbb }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8608 }, + { 0xa438, 0x9503 }, { 0xa438, 0x1000 }, { 0xa438, 0x0d8f }, + { 0xa438, 0xd704 }, { 0xa438, 0x7fb6 }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0x87f0 }, { 0xa438, 0x9503 }, + { 0xa438, 0xce88 }, { 0xa438, 0x1000 }, { 0xa438, 0x117a }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0xa608 }, + { 0xa438, 0x9503 }, { 0xa438, 0xd73e }, { 0xa438, 0x60a5 }, + { 0xa438, 0xd705 }, { 0xa438, 0x4071 }, { 0xa438, 0x1800 }, + { 0xa438, 0x0d65 }, { 0xa438, 0x1800 }, { 0xa438, 0x0d6f }, + { 0xa436, 0xa10e }, { 0xa438, 0x0d58 }, { 0xa436, 0xa10c }, + { 0xa438, 0x0cb5 }, { 0xa436, 0xa10a }, { 0xa438, 0x0bd1 }, + { 0xa436, 0xa108 }, { 0xa438, 0x0e37 }, { 0xa436, 0xa106 }, + { 0xa438, 0x1267 }, { 0xa436, 0xa104 }, { 0xa438, 0x0b3b }, + { 0xa436, 0xa102 }, { 0xa438, 0x0c38 }, { 0xa436, 0xa100 }, + { 0xa438, 0x0c24 }, { 0xa436, 0xa110 }, { 0xa438, 0x00ff }, + { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, + { 0xa438, 0x1ff8 }, { 0xa436, 0xa014 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa164 }, { 0xa438, 0x0ceb }, + { 0xa436, 0xa166 }, { 0xa438, 0x0e73 }, { 0xa436, 0xa168 }, + { 0xa438, 0x0deb }, { 0xa436, 0xa16a }, { 0xa438, 0x3fff }, + { 0xa436, 0xa16c }, { 0xa438, 0x3fff }, { 0xa436, 0xa16e }, + { 0xa438, 0x3fff }, { 0xa436, 0xa170 }, { 0xa438, 0x3fff }, + { 0xa436, 0xa172 }, { 0xa438, 0x3fff }, { 0xa436, 0xa162 }, + { 0xa438, 0x0007 }, { 0xa436, 0xb87c }, { 0xa438, 0x85bf }, + { 0xa436, 0xb87e }, { 0xa438, 0xaf85 }, { 0xa438, 0xd7af }, + { 0xa438, 0x85fb }, { 0xa438, 0xaf86 }, { 0xa438, 0x10af }, + { 0xa438, 0x8638 }, { 0xa438, 0xaf86 }, { 0xa438, 0x47af }, + { 0xa438, 0x8647 }, { 0xa438, 0xaf86 }, { 0xa438, 0x47af }, + { 0xa438, 0x8647 }, { 0xa438, 0xbf85 }, { 0xa438, 0xf802 }, + { 0xa438, 0x627f }, { 0xa438, 0xbf61 }, { 0xa438, 0xc702 }, + { 0xa438, 0x627f }, { 0xa438, 0xae0c }, { 0xa438, 0xbf85 }, + { 0xa438, 0xf802 }, { 0xa438, 0x6276 }, { 0xa438, 0xbf61 }, + { 0xa438, 0xc702 }, { 0xa438, 0x6276 }, { 0xa438, 0xee85 }, + { 0xa438, 0x4200 }, { 0xa438, 0xaf1b }, { 0xa438, 0x2333 }, + { 0xa438, 0xa484 }, { 0xa438, 0xbf86 }, { 0xa438, 0x0a02 }, + { 0xa438, 0x627f }, { 0xa438, 0xbf86 }, { 0xa438, 0x0d02 }, + { 0xa438, 0x627f }, { 0xa438, 0xaf1b }, { 0xa438, 0x8422 }, + { 0xa438, 0xa484 }, { 0xa438, 0x66ac }, { 0xa438, 0x0ef8 }, + { 0xa438, 0xfbef }, { 0xa438, 0x79fb }, { 0xa438, 0xe080 }, + { 0xa438, 0x16ad }, { 0xa438, 0x230f }, { 0xa438, 0xee85 }, + { 0xa438, 0x4200 }, { 0xa438, 0x1f44 }, { 0xa438, 0xbf86 }, + { 0xa438, 0x30d7 }, { 0xa438, 0x0008 }, { 0xa438, 0x0264 }, + { 0xa438, 0xa3ff }, { 0xa438, 0xef97 }, { 0xa438, 0xfffc }, + { 0xa438, 0x0485 }, { 0xa438, 0xf861 }, { 0xa438, 0xc786 }, + { 0xa438, 0x0a86 }, { 0xa438, 0x0de1 }, { 0xa438, 0x8feb }, + { 0xa438, 0xe583 }, { 0xa438, 0x20e1 }, { 0xa438, 0x8fea }, + { 0xa438, 0xe583 }, { 0xa438, 0x21af }, { 0xa438, 0x41a7 }, + { 0xa436, 0xb85e }, { 0xa438, 0x1b05 }, { 0xa436, 0xb860 }, + { 0xa438, 0x1b78 }, { 0xa436, 0xb862 }, { 0xa438, 0x1a08 }, + { 0xa436, 0xb864 }, { 0xa438, 0x419f }, { 0xa436, 0xb886 }, + { 0xa438, 0xffff }, { 0xa436, 0xb888 }, { 0xa438, 0xffff }, + { 0xa436, 0xb88a }, { 0xa438, 0xffff }, { 0xa436, 0xb88c }, + { 0xa438, 0xffff }, { 0xa436, 0xb838 }, { 0xa438, 0x000f }, + { 0xb820, 0x0010 }, { 0xa436, 0x0000 }, { 0xa438, 0x0000 }, + { 0xb82e, 0x0000 }, { 0xa436, 0x8023 }, { 0xa438, 0x0000 }, + { 0xa436, 0x801e }, { 0xa438, 0x0013 }, { 0xb820, 0x0000 }, + { 0xa436, 0xacca }, { 0xa438, 0x0104 }, { 0xa436, 0xaccc }, + { 0xa438, 0x8000 }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0fff }, { 0xa436, 0xacce }, + { 0xa438, 0xfd47 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0fff }, + { 0xa436, 0xacce }, { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xe56f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01c0 }, { 0xa436, 0xacce }, + { 0xa438, 0xffff }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xed97 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01c8 }, { 0xa436, 0xacce }, { 0xa438, 0xffff }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xf5bf }, { 0xa436, 0xacd0 }, { 0xa438, 0x01d0 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb07 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb0f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01d8 }, { 0xa436, 0xacce }, + { 0xa438, 0xa087 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, + { 0xa436, 0xacce }, { 0xa438, 0xa00f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0108 }, { 0xa436, 0xacce }, { 0xa438, 0xa807 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0100 }, { 0xa436, 0xacce }, + { 0xa438, 0xa88f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, + { 0xa436, 0xacce }, { 0xa438, 0xb027 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0120 }, { 0xa436, 0xacce }, { 0xa438, 0xb02f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0128 }, { 0xa436, 0xacce }, + { 0xa438, 0xb847 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, + { 0xa436, 0xacce }, { 0xa438, 0xb84f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0148 }, { 0xa436, 0xacce }, { 0xa438, 0xfb17 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb1f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xa017 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0110 }, { 0xa436, 0xacce }, { 0xa438, 0xa01f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, { 0xa436, 0xacce }, + { 0xa438, 0xa837 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, + { 0xa436, 0xacce }, { 0xa438, 0xa83f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0138 }, { 0xa436, 0xacce }, { 0xa438, 0xb097 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, { 0xa436, 0xacce }, + { 0xa438, 0xb05f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, + { 0xa436, 0xacce }, { 0xa438, 0xb857 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0150 }, { 0xa436, 0xacce }, { 0xa438, 0xb89f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb27 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb2f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x8087 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, { 0xa436, 0xacce }, + { 0xa438, 0x800f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, + { 0xa436, 0xacce }, { 0xa438, 0x8807 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0100 }, { 0xa436, 0xacce }, { 0xa438, 0x888f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, { 0xa436, 0xacce }, + { 0xa438, 0x9027 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, + { 0xa436, 0xacce }, { 0xa438, 0x902f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0128 }, { 0xa436, 0xacce }, { 0xa438, 0x9847 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, { 0xa436, 0xacce }, + { 0xa438, 0x984f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, + { 0xa436, 0xacce }, { 0xa438, 0xa0a7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, { 0xa438, 0xa8af }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, + { 0xa438, 0xa067 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, + { 0xa436, 0xacce }, { 0xa438, 0xa86f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0169 }, { 0xa436, 0xacce }, { 0xa438, 0xfb37 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb3f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x8017 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0110 }, { 0xa436, 0xacce }, { 0xa438, 0x801f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, { 0xa436, 0xacce }, + { 0xa438, 0x8837 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, + { 0xa436, 0xacce }, { 0xa438, 0x883f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0138 }, { 0xa436, 0xacce }, { 0xa438, 0x9097 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, { 0xa436, 0xacce }, + { 0xa438, 0x905f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, + { 0xa436, 0xacce }, { 0xa438, 0x9857 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0150 }, { 0xa436, 0xacce }, { 0xa438, 0x989f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, { 0xa436, 0xacce }, + { 0xa438, 0xb0b7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, + { 0xa436, 0xacce }, { 0xa438, 0xb8bf }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, { 0xa438, 0xb077 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, { 0xa436, 0xacce }, + { 0xa438, 0xb87f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb47 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb4f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0x6087 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0180 }, + { 0xa436, 0xacce }, { 0xa438, 0x600f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0108 }, { 0xa436, 0xacce }, { 0xa438, 0x6807 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0100 }, { 0xa436, 0xacce }, + { 0xa438, 0x688f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0188 }, + { 0xa436, 0xacce }, { 0xa438, 0x7027 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0120 }, { 0xa436, 0xacce }, { 0xa438, 0x702f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0128 }, { 0xa436, 0xacce }, + { 0xa438, 0x7847 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0140 }, + { 0xa436, 0xacce }, { 0xa438, 0x784f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0148 }, { 0xa436, 0xacce }, { 0xa438, 0x80a7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, + { 0xa438, 0x88af }, { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, + { 0xa436, 0xacce }, { 0xa438, 0x8067 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0161 }, { 0xa436, 0xacce }, { 0xa438, 0x886f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb57 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb5f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x6017 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0110 }, { 0xa436, 0xacce }, + { 0xa438, 0x601f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0118 }, + { 0xa436, 0xacce }, { 0xa438, 0x6837 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0130 }, { 0xa436, 0xacce }, { 0xa438, 0x683f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0138 }, { 0xa436, 0xacce }, + { 0xa438, 0x7097 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0190 }, + { 0xa436, 0xacce }, { 0xa438, 0x705f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0158 }, { 0xa436, 0xacce }, { 0xa438, 0x7857 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0150 }, { 0xa436, 0xacce }, + { 0xa438, 0x789f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0198 }, + { 0xa436, 0xacce }, { 0xa438, 0x90b7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, { 0xa438, 0x98bf }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, { 0xa436, 0xacce }, + { 0xa438, 0x9077 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, + { 0xa436, 0xacce }, { 0xa438, 0x987f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0179 }, { 0xa436, 0xacce }, { 0xa438, 0xfb67 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfb6f }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0x4087 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0180 }, { 0xa436, 0xacce }, { 0xa438, 0x400f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0108 }, { 0xa436, 0xacce }, + { 0xa438, 0x4807 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0100 }, + { 0xa436, 0xacce }, { 0xa438, 0x488f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0188 }, { 0xa436, 0xacce }, { 0xa438, 0x5027 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0120 }, { 0xa436, 0xacce }, + { 0xa438, 0x502f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0128 }, + { 0xa436, 0xacce }, { 0xa438, 0x5847 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0140 }, { 0xa436, 0xacce }, { 0xa438, 0x584f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0148 }, { 0xa436, 0xacce }, + { 0xa438, 0x60a7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x01a0 }, + { 0xa436, 0xacce }, { 0xa438, 0x68af }, { 0xa436, 0xacd0 }, + { 0xa438, 0x01a8 }, { 0xa436, 0xacce }, { 0xa438, 0x6067 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, { 0xa436, 0xacce }, + { 0xa438, 0x686f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, + { 0xa436, 0xacce }, { 0xa438, 0xfb77 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfb7f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0x4017 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0110 }, + { 0xa436, 0xacce }, { 0xa438, 0x401f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0118 }, { 0xa436, 0xacce }, { 0xa438, 0x4837 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0130 }, { 0xa436, 0xacce }, + { 0xa438, 0x483f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0138 }, + { 0xa436, 0xacce }, { 0xa438, 0x5097 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0190 }, { 0xa436, 0xacce }, { 0xa438, 0x505f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0158 }, { 0xa436, 0xacce }, + { 0xa438, 0x5857 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0150 }, + { 0xa436, 0xacce }, { 0xa438, 0x589f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0198 }, { 0xa436, 0xacce }, { 0xa438, 0x70b7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, + { 0xa438, 0x78bf }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, + { 0xa436, 0xacce }, { 0xa438, 0x7077 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0171 }, { 0xa436, 0xacce }, { 0xa438, 0x787f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb87 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb8f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x40a7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01a0 }, { 0xa436, 0xacce }, + { 0xa438, 0x48af }, { 0xa436, 0xacd0 }, { 0xa438, 0x01a8 }, + { 0xa436, 0xacce }, { 0xa438, 0x4067 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0161 }, { 0xa436, 0xacce }, { 0xa438, 0x486f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, { 0xa436, 0xacce }, + { 0xa438, 0xfb97 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfb9f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x50b7 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x01b0 }, { 0xa436, 0xacce }, + { 0xa438, 0x58bf }, { 0xa436, 0xacd0 }, { 0xa438, 0x01b8 }, + { 0xa436, 0xacce }, { 0xa438, 0x5077 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0171 }, { 0xa436, 0xacce }, { 0xa438, 0x587f }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0179 }, { 0xa436, 0xacce }, + { 0xa438, 0xfba7 }, { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, + { 0xa436, 0xacce }, { 0xa438, 0xfbaf }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0x2067 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x0161 }, { 0xa436, 0xacce }, + { 0xa438, 0x286f }, { 0xa436, 0xacd0 }, { 0xa438, 0x0169 }, + { 0xa436, 0xacce }, { 0xa438, 0xfbb7 }, { 0xa436, 0xacd0 }, + { 0xa438, 0x07ff }, { 0xa436, 0xacce }, { 0xa438, 0xfbbf }, + { 0xa436, 0xacd0 }, { 0xa438, 0x07ff }, { 0xa436, 0xacce }, + { 0xa438, 0x3077 }, { 0xa436, 0xacd0 }, { 0xa438, 0x0171 }, + { 0xa436, 0xacce }, { 0xa438, 0x387f }, { 0xa436, 0xacd0 }, + { 0xa438, 0x0179 }, { 0xa436, 0xacce }, { 0xa438, 0xfff9 }, + { 0xa436, 0xacd0 }, { 0xa438, 0x17ff }, { 0xa436, 0xacce }, + { 0xa438, 0xfff9 }, { 0xa436, 0xacd0 }, { 0xa438, 0x17ff }, + { 0xa436, 0xacca }, { 0xa438, 0x0004 }, { 0xa436, 0xacc6 }, + { 0xa438, 0x0008 }, { 0xa436, 0xacc8 }, { 0xa438, 0xc000 }, + { 0xa436, 0xacc8 }, { 0xa438, 0x0000 }, { 0xb820, 0x0000 } +}; diff --git a/drivers/net/r8169/firmware_8125.h b/drivers/net/r8169/firmware_8125.h new file mode 100644 index 00000000..f9f3319a --- /dev/null +++ b/drivers/net/r8169/firmware_8125.h @@ -0,0 +1,13 @@ +/* Firmware data declarations; data copyright and distribution notice in firmware_8125.c. */ +#ifndef RELIEFNT_RTL8125_FIRMWARE_H +#define RELIEFNT_RTL8125_FIRMWARE_H +#include +struct rtl8125_fw_pair { uint16_t reg; uint16_t val; }; +extern const struct rtl8125_fw_pair rtl8125_mac_bps[256]; +extern const struct rtl8125_fw_pair rtl8125b_mac_bps[138]; +extern const struct rtl8125_fw_pair rtl8125d_2_mac_bps[66]; +extern const struct rtl8125_fw_pair mac_r25_mcu[550]; +extern const struct rtl8125_fw_pair mac_r25b_mcu[1447]; +extern const struct rtl8125_fw_pair mac_r25d_1_mcu[3241]; +extern const struct rtl8125_fw_pair mac_r25d_2_mcu[1818]; +#endif diff --git a/drivers/net/r8169/hardware.c b/drivers/net/r8169/hardware.c new file mode 100644 index 00000000..79556668 --- /dev/null +++ b/drivers/net/r8169/hardware.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "internal.h" + +/** @brief Enter PCI D0 through the bounded conventional capability chain. + * @param d PCI device with bus mastering disabled. + * @return Zero, or -EINVAL for a corrupt chain or unsupported header type. + */ +static int enter_d0(struct rtl_device *d) +{ + const struct reliefos_driver_pci_device *p = &d->pci; + if ((p->header_type & 0x7f) != 0) + return -22; + if (!(d->api->pci_read16(p->bus, p->slot, p->function, 6) & 0x10)) + return 0; + uint8_t next = d->api->pci_read32(p->bus, p->slot, p->function, 0x34) & 0xff; + uint64_t visited = 0; + while (next) { + if (next < 0x40 || next > 0xfc || (next & 3)) + return -22; + uint64_t bit = 1ULL << (next / 4); + if (visited & bit) + return -22; + visited |= bit; + uint16_t cap = d->api->pci_read16(p->bus, p->slot, p->function, next); + if ((cap & 0xff) == 1) { + if (next > 0xf8) + return -22; + uint16_t power = d->api->pci_read16(p->bus, p->slot, p->function, next + 4); + /* PME status is W1C. Preserve it while requesting standard D0. */ + d->api->pci_write16(p->bus, p->slot, p->function, next + 4, + power & ~(0x8000u | 3u)); + rtl_delay_us(d, 10000); + if (d->api->pci_read16(p->bus, p->slot, p->function, next + 4) & 3) + return -5; + return 0; + } + next = cap >> 8; + } + return 0; +} + +/** @brief Map the preferred register BAR, trying other memory BARs when necessary. + * @param d Bound PCI function retaining the successful MMIO lease. + * @return Zero, -EINVAL for no usable memory BAR, or -ENOMEM if all leases fail. + */ +static int map_registers(struct rtl_device *d) +{ + const struct reliefos_driver_pci_device *p = &d->pci; + uint64_t bases[6] = {0}; + uint16_t io_base = 0; + for (unsigned index = 0; index < 6; ++index) { + unsigned bar_index = index; + unsigned offset = 0x10 + index * 4; + uint32_t low = d->api->pci_read32(p->bus, p->slot, p->function, offset); + if (!low || low == UINT32_MAX) + continue; + if (low & 1) { + uint32_t port = low & ~3u; + if (bar_index == 0 && port && !(port & 0xffu) && port <= 0xff00u) + io_base = port; + continue; + } + uint64_t base = low & ~0xfu; + if ((low & 6) == 4) { + if (index == 5) + continue; + base |= (uint64_t)d->api->pci_read32(p->bus, p->slot, p->function, + offset + 4) << 32; + ++index; + } else if (low & 6) { + continue; + } + if (!base || (base & 4095u) || base > UINT64_MAX - d->mmio_bytes) + continue; + bases[bar_index] = base; + } + /* BAR2 is the full PCIe register aperture on modern Realtek controllers. */ + static const unsigned preference[] = {2, 1, 0, 4, 3, 5}; + int rc = -22; + for (unsigned i = 0; i < sizeof(preference) / sizeof(preference[0]); ++i) { + uint64_t base = bases[preference[i]]; + if (!base) + continue; + d->registers = d->api->map_mmio(base, d->mmio_bytes); + if (d->registers) + return 0; + rc = -12; + } + /* Older RTL8168 has a 256-byte control BAR. Its I/O BAR provides the + * same registers without mapping pages outside the implemented aperture. */ + if (d->family == RTL_FAMILY_8168 && io_base && d->api->inb && d->api->outb && + d->api->inl && d->api->outl) { + d->io_base = io_base; + d->mmio_bytes = 0x100; + return 0; + } + return rc; +} + +/** @brief Discover a supported Realtek function and retain its MMIO/PCI state. + * @param d Zeroed device containing validated kernel services. + * @return Zero with identified hardware and valid station address, or negative errno. + * Bus mastering remains disabled until rings have been fully allocated. + */ +int rtl_hardware_probe(struct rtl_device *d) +{ + static const uint16_t ids[] = {0x8168, 0x8125}; + for (unsigned i = 0; i < sizeof(ids) / sizeof(ids[0]); ++i) { + if (!d->api->pci_find(0x10ec, ids[i], &d->pci)) { + d->present = true; + break; + } + } + if (!d->present) + return -19; + const struct reliefos_driver_pci_device *p = &d->pci; + if (p->class_code != 2 || p->subclass != 0) + return -19; + d->family = p->device_id == 0x8125 ? RTL_FAMILY_8125 : RTL_FAMILY_8168; + d->mmio_bytes = d->family == RTL_FAMILY_8125 ? 0x10000 : 0x1000; + d->original_command = d->api->pci_read16(p->bus, p->slot, p->function, 4); + d->command_saved = true; + d->api->pci_write16(p->bus, p->slot, p->function, 4, + (d->original_command & ~7u) | (1u << 10)); + int rc = enter_d0(d); + if (rc) + return rc; + rc = map_registers(d); + if (rc) + return rc; + d->api->pci_write16(p->bus, p->slot, p->function, 4, + (d->original_command & ~7u) | (d->io_base ? 1u : 2u) | (1u << 10)); + d->xid = rtl_read32(d, 0x40) & 0x7cf00000u; + rc = d->family == RTL_FAMILY_8125 ? rtl8125_identify(d) : rtl8168_identify(d); + if (rc) { + d->api->console_log(CONSOLE_LOG_WARN, + "[r8169] unsupported Realtek %04x:%04x XID=%08x\n", + p->vendor_id, p->device_id, d->xid); + return rc; + } + /* The firmware-loaded station address is retained before MAC reset. */ + unsigned mac_offset = d->family == RTL_FAMILY_8125 ? 0x19e0 : 0; + uint32_t low = rtl_read32(d, mac_offset); + uint16_t high = d->family == RTL_FAMILY_8125 ? rtl_read16(d, mac_offset + 4) : + (uint16_t)rtl_read32(d, mac_offset + 4); + for (unsigned i = 0; i < 4; ++i) + d->mac[i] = low >> (i * 8); + d->mac[4] = high; + d->mac[5] = high >> 8; + unsigned any = 0; + for (unsigned i = 0; i < 6; ++i) + any |= d->mac[i]; + if (!any || (d->mac[0] & 1)) + return -5; + return 0; +} + +/** @brief Confirm controller reset and close PCI bus-master admission. + * @param d Device with callback users drained; partial probe is accepted. + * @return Zero if allocations may be released, or negative errno retaining them. + */ +int rtl_hardware_stop(struct rtl_device *d) +{ + d->active = false; + int rc = 0; + if ((d->registers || d->io_base) && d->chip_name) { + /* Clear a previous initialization timeout before attempting recovery. */ + d->io_error = 0; + rc = d->family == RTL_FAMILY_8125 ? rtl8125_stop(d) : rtl8168_stop(d); + } + if (d->command_saved) { + const struct reliefos_driver_pci_device *p = &d->pci; + uint16_t command = d->api->pci_read16(p->bus, p->slot, p->function, 4); + d->api->pci_write16(p->bus, p->slot, p->function, 4, command & ~4u); + if (d->api->pci_read16(p->bus, p->slot, p->function, 4) & 4) + rc = -5; + } + return rc; +} diff --git a/drivers/net/r8169/internal.h b/drivers/net/r8169/internal.h new file mode 100644 index 00000000..1313a9c2 --- /dev/null +++ b/drivers/net/r8169/internal.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#ifndef RELIEFNT_R8169_INTERNAL_H +#define RELIEFNT_R8169_INTERNAL_H + +#include +#include + +#define RTL_RX_COUNT 256u +#define RTL_TX_COUNT 256u +#define RTL_BUFFER_SIZE 2048u +#define RTL_MAX_FRAME 1518u +#define RTL_RX_PAGES (RTL_RX_COUNT * RTL_BUFFER_SIZE / 4096u) +#define RTL_TX_PAGES (RTL_TX_COUNT * RTL_BUFFER_SIZE / 4096u) +#define RTL_DESC_OWN (1u << 31) +#define RTL_DESC_EOR (1u << 30) +#define RTL_DESC_FIRST (1u << 29) +#define RTL_DESC_LAST (1u << 28) +#define RTL_RX_ERROR (1u << 21) + +enum rtl_family { RTL_FAMILY_8168, RTL_FAMILY_8125 }; + +struct rtl_descriptor { + uint32_t command; + uint32_t options; + uint64_t address; +} __attribute__((aligned(16))); + +_Static_assert(sizeof(struct rtl_descriptor) == 16, "Realtek descriptor size"); +_Static_assert(RTL_RX_COUNT * sizeof(struct rtl_descriptor) == 4096, "RX ring page"); +_Static_assert(RTL_TX_COUNT * sizeof(struct rtl_descriptor) == 4096, "TX ring page"); + +struct rtl_device { + const struct reliefos_driver_kernel_api *api; + struct reliefos_driver_pci_device pci; + volatile uint8_t *registers; + uint32_t mmio_bytes; + uint32_t xid; + enum rtl_family family; + unsigned chip_revision; + const char *chip_name; + uint32_t quirks; + int io_error; + uint16_t original_command; + uint16_t io_base; + bool command_saved; + bool present; + bool active; + bool dropping_fragments; + uint8_t mac[6]; + uint64_t rx_physical, tx_physical, rx_data_physical, tx_data_physical; + volatile struct rtl_descriptor *rx, *tx; + uint8_t *rx_data, *tx_data; + unsigned rx_next, tx_next, tx_clean; + struct kernel_spinlock rx_lock, tx_lock; +}; + +/** @brief Read one byte from the device's memory or legacy I/O BAR. + * @param d Bound device. @param offset Register offset within mmio_bytes. + * @return Hardware register byte. No allocation or scheduling. + */ +uint8_t rtl_read8(const struct rtl_device *d, unsigned offset); +/** @brief Read an aligned little-endian 16-bit device register. + * @param d Bound device. @param offset In-range even byte offset. + * @return Hardware register value. No allocation or scheduling. + */ +uint16_t rtl_read16(const struct rtl_device *d, unsigned offset); +/** @brief Read an aligned little-endian 32-bit device register. + * @param d Bound device. @param offset In-range aligned byte offset. + * @return Hardware register value. No allocation or scheduling. + */ +uint32_t rtl_read32(const struct rtl_device *d, unsigned offset); +/** @brief Write one byte through the live device MMIO lease. + * @param d Bound device. @param offset In-range offset. @param value Register value. + */ +void rtl_write8(struct rtl_device *d, unsigned offset, uint8_t value); +/** @brief Write an aligned 16-bit device register without scheduling. + * @param d Bound device. @param offset In-range even offset. @param value Register value. + */ +void rtl_write16(struct rtl_device *d, unsigned offset, uint16_t value); +/** @brief Write an aligned 32-bit device register without scheduling. + * @param d Bound device. @param offset In-range aligned offset. @param value Register value. + */ +void rtl_write32(struct rtl_device *d, unsigned offset, uint32_t value); +/** @brief Provide the requested settling delay in initialization context. + * @param d Bound device with sleep service. @param microseconds Minimum wait. + * Uses bounded boot-uptime polling or tick sleep; no spinlock may be held. + * Short-wait accuracy depends on the boot clock. + * A sleep can temporarily enable interrupts; entry IRQ state is restored. + */ +void rtl_delay_us(struct rtl_device *d, unsigned microseconds); + +/** @brief Identify a supported RTL8111/8168 MAC by its TxConfig XID. + * @param d Mapped device with xid read before any hardware reset. + * @return Zero with chip metadata, or -ENODEV for an unrecognized revision. + */ +int rtl8168_identify(struct rtl_device *d); +/** @brief Configure the gigabit MAC, PHY and the already allocated DMA rings. + * @param d Identified mapped device with coherent rings and PCI bus mastering enabled. + * @return Zero with RX/TX running, or negative errno retaining resources for stop. + */ +int rtl8168_start(struct rtl_device *d); +/** @brief Quiesce and reset the gigabit MAC before releasing any DMA memory. + * @param d Identified device, including partially initialized state. + * @return Zero on confirmed reset, or negative errno requiring resource retention. + */ +int rtl8168_stop(struct rtl_device *d); + +/** @brief Identify a supported RTL8125 MAC using TxConfig's hardware revision. + * @param d Mapped device with xid set before reset. + * @return Zero with chip metadata, or -ENODEV for unsupported silicon. + */ +int rtl8125_identify(struct rtl_device *d); +/** @brief Load the matching firmware and configure one standard RX/TX queue. + * @param d Identified mapped device with rings and PCI bus mastering enabled. + * @return Zero with RX/TX running, or negative errno retaining all resources. + */ +int rtl8125_start(struct rtl_device *d); +/** @brief Disable and reset RTL8125 DMA before the owner releases its resources. + * @param d Identified mapped device, including partial initialization. + * @return Zero on confirmed quiescence, or negative errno requiring retention. + */ +int rtl8125_stop(struct rtl_device *d); + +/** @brief Probe a supported PCI identity, enter D0, claim a BAR and identify the MAC. + * @param d Zeroed state with validated services; retained for mandatory rollback. + * @return Zero or negative Linux errno. Leaves bus mastering disabled. + */ +int rtl_hardware_probe(struct rtl_device *d); +/** @brief Stop controller DMA and disable PCI bus mastering before release. + * @param d Owned initialized or partial device with callbacks drained. + * @return Zero on confirmed STOP or negative errno requiring resource retention. + */ +int rtl_hardware_stop(struct rtl_device *d); +/** @brief Allocate coherent RX/TX descriptors and packet backing. + * @param d Stopped device; successful partial allocations remain in state. + * @return Zero or -ENOMEM; physical addresses are device DMA addresses. + */ +int rtl_allocate_rings(struct rtl_device *d); +/** @brief Release retained DMA allocations after confirmed device STOP. + * @param d Quiescent device, including partial allocation state. + */ +void rtl_free_rings(struct rtl_device *d); +/** @brief Queue an Ethernet frame without waiting for hardware completion. + * @param d Active pinned device. @param frame Borrowed bytes. @param length Excludes FCS. + * @return Zero on admission or negative errno including -EAGAIN when full. + */ +int rtl_send(struct rtl_device *d, const void *frame, uint32_t length); +/** @brief Consume at most one completed RX descriptor and recycle it safely. + * @param d Active pinned device. @param frame Output buffer. @param capacity Buffer size. + * @param length Optional output, cleared on empty/error; successful size excludes FCS. + * @return One for a frame, zero for empty, or negative Linux errno. + */ +int rtl_receive(struct rtl_device *d, void *frame, uint32_t capacity, uint32_t *length); + +#endif diff --git a/drivers/net/r8169/io.c b/drivers/net/r8169/io.c new file mode 100644 index 00000000..9bd366cc --- /dev/null +++ b/drivers/net/r8169/io.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "internal.h" +#include +#include + +/** @brief Read a device byte through its owned UC mapping. + * @param d Mapped device. @param offset In-range byte offset. @return Register value. + */ +uint8_t rtl_read8(const struct rtl_device *d, unsigned offset) +{ + if (d->io_base) + return d->api->inb(d->io_base + offset); + return *(volatile uint8_t *)(d->registers + offset); +} + +/** @brief Read an aligned device word through its owned UC mapping. + * @param d Mapped device. @param offset In-range even offset. @return Register value. + */ +uint16_t rtl_read16(const struct rtl_device *d, unsigned offset) +{ + if (d->io_base) + return x86_64_inw(d->io_base + offset); + return *(volatile uint16_t *)(d->registers + offset); +} + +/** @brief Read an aligned device dword through its owned UC mapping. + * @param d Mapped device. @param offset In-range aligned offset. @return Register value. + */ +uint32_t rtl_read32(const struct rtl_device *d, unsigned offset) +{ + if (d->io_base) + return d->api->inl(d->io_base + offset); + return *(volatile uint32_t *)(d->registers + offset); +} + +/** @brief Issue a byte write without sleeping or acquiring locks. + * @param d Mapped device. @param offset In-range offset. @param value Register value. + */ +void rtl_write8(struct rtl_device *d, unsigned offset, uint8_t value) +{ + if (d->io_base) { + d->api->outb(d->io_base + offset, value); + return; + } + *(volatile uint8_t *)(d->registers + offset) = value; +} + +/** @brief Issue a word write without sleeping or acquiring locks. + * @param d Mapped device. @param offset In-range even offset. @param value Register value. + */ +void rtl_write16(struct rtl_device *d, unsigned offset, uint16_t value) +{ + if (d->io_base) { + x86_64_outw(value, d->io_base + offset); + return; + } + *(volatile uint16_t *)(d->registers + offset) = value; +} + +/** @brief Issue a dword write without sleeping or acquiring locks. + * @param d Mapped device. @param offset In-range aligned offset. @param value Register value. + */ +void rtl_write32(struct rtl_device *d, unsigned offset, uint32_t value) +{ + if (d->io_base) { + d->api->outl(d->io_base + offset, value); + return; + } + *(volatile uint32_t *)(d->registers + offset) = value; +} + +/** @brief Provide a settling delay while initialization owns the hardware. + * @param d Device with validated sleep callback. @param microseconds Minimum interval. + * Caller holds no spinlock. Short waits pin the CPU with IRQs masked and poll + * boot uptime; bounded failure or longer waits use the tick sleep service, + * which temporarily permits interrupts. The caller's IRQ state is restored. + */ +void rtl_delay_us(struct rtl_device *d, unsigned microseconds) +{ + uint64_t flags; + + if (!microseconds) + return; + + /* NULL saves IRQ state without acquiring a lock. This pins the short + * clock comparison to one CPU, while allowing the fallback to sleep. */ + kernel_spin_lock_irqsave(NULL, &flags); + if (microseconds < 1000u) { + uint64_t start = time_uptime_us(); + uint64_t previous = start; + + /* Uptime can stop at a pending tick, or regress after PIT rollover. + * The extra microsecond covers truncation at both sample boundaries. */ + for (unsigned samples = 0; samples < 4096u; ++samples) { + uint64_t now = time_uptime_us(); + if (now < previous) + break; + if (now - start >= (uint64_t)microseconds + 1u) { + kernel_spin_unlock_irqrestore(NULL, flags); + return; + } + previous = now; + __asm__ volatile("pause" : : : "memory"); + } + } + + /* A tick sleep can start just before its first tick. One extra whole tick + * ensures the remaining ticks cover at least the requested interval. */ + uint64_t milliseconds = ((uint64_t)microseconds + 999u) / 1000u; + milliseconds += (1000u + RELIEFNT_TICK_HZ - 1u) / RELIEFNT_TICK_HZ; + d->api->sleep_ms(milliseconds); + kernel_spin_unlock_irqrestore(NULL, flags); +} diff --git a/drivers/net/r8169/main.c b/drivers/net/r8169/main.c new file mode 100644 index 00000000..a2bd84c9 --- /dev/null +++ b/drivers/net/r8169/main.c @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "internal.h" + +static struct rtl_device device; + +/** @brief Observe the hardware's current link indication without MDIO waits. + * @return Nonzero only for an active bound controller with a copper link. + */ +static int ready(void) +{ + return device.active && (rtl_read8(&device, 0x6c) & 2); +} + +/** @brief Borrow the immutable station address while the caller holds its owner pin. + * @return Device-owned six-byte station address, retained until callback drain. + */ +static const uint8_t *mac(void) +{ + return device.mac; +} + +/** @brief Submit a frame through the retained single-interface network service. + * @param frame Borrowed Ethernet bytes. @param length Size excluding FCS. + * @return Zero on admission or negative Linux errno without waiting. + */ +static int send(const void *frame, uint32_t length) +{ + return rtl_send(&device, frame, length); +} + +/** @brief Consume one descriptor through the retained network service. + * @param frame Writable output. @param capacity Buffer capacity. @param length Optional size output. + * @return One for a frame, zero if empty, or negative Linux errno. + */ +static int receive(void *frame, uint32_t capacity, uint32_t *length) +{ + return rtl_receive(&device, frame, capacity, length); +} + +/** @brief Report the actual PCI identity, link state and station address. + * @param out Nullable caller-owned output; no private pointer crosses the interface. + */ +static void info(struct reliefos_driver_e1000_info *out) +{ + if (!out) + return; + *out = (struct reliefos_driver_e1000_info){ + .present = device.present, .active = ready() != 0, + .vendor_id = device.pci.vendor_id, .device_id = device.pci.device_id, + .bus = device.pci.bus, .slot = device.pci.slot, .function = device.pci.function + }; + for (unsigned i = 0; i < 6; ++i) + out->mac[i] = device.mac[i]; +} + +/** @brief Initialize a supported Realtek MAC and publish its owner-pinned callbacks. + * @param api Size/version-qualified services borrowed for the binding's lifetime. + * @return Zero or negative Linux errno; partial resources remain for mandatory fini. + */ +static int start(const struct reliefos_driver_kernel_api *api) +{ + static const struct reliefos_driver_e1000_ops ops = {ready, mac, send, receive, info}; + if (!api || api->abi_version != RELIEFOS_DRIVER_ABI_VERSION || + api->struct_size < RELIEFOS_DRIVER_PHYS_MAP_API_SIZE || + !api->pci_find || !api->pci_read16 || !api->pci_write16 || !api->pci_read32 || + !api->map_mmio || !api->unmap_mmio || !api->alloc_dma || !api->free_dma || + !api->phys_to_virt || !api->sleep_ms || !api->register_e1000 || + !api->console_log || !api->report_teardown_failure) + return -22; + device = (struct rtl_device){.api = api}; + int rc = rtl_hardware_probe(&device); + if (rc) + return rc; + rc = rtl_hardware_stop(&device); + if (rc) + return rc; + rc = rtl_allocate_rings(&device); + if (rc) + return rc; + const struct reliefos_driver_pci_device *p = &device.pci; + uint16_t command = api->pci_read16(p->bus, p->slot, p->function, 4); + api->pci_write16(p->bus, p->slot, p->function, 4, command | 4u); + if (!(api->pci_read16(p->bus, p->slot, p->function, 4) & 4)) + return -5; + rc = device.family == RTL_FAMILY_8125 ? rtl8125_start(&device) : rtl8168_start(&device); + if (rc) + return rc; + device.active = true; + rc = api->register_e1000(&ops); + if (rc) + return rc; + api->console_log(CONSOLE_LOG_INFO, + "[r8169] %02x:%02x.%u %s %04x:%04x XID=%08x MAC=%02x:%02x:%02x:%02x:%02x:%02x; link=%s\n", + p->bus, p->slot, p->function, device.chip_name, p->vendor_id, p->device_id, device.xid, + device.mac[0], device.mac[1], device.mac[2], device.mac[3], device.mac[4], device.mac[5], + ready() ? "up" : "negotiating/down"); + return 0; +} + +/** @brief Stop and drain hardware before relinquishing owned MMIO and DMA backing. + * A failed reset retains the resources and module through the manager's retry contract. + * Called only after callback admission closes and all outstanding users drain. + */ +static void stop(void) +{ + if (!device.api) + return; + int rc = rtl_hardware_stop(&device); + if (rc) { + device.api->report_teardown_failure(rc); + return; + } + rtl_free_rings(&device); + if (device.registers) + device.api->unmap_mmio((void *)device.registers, device.mmio_bytes); + if (device.command_saved) { + const struct reliefos_driver_pci_device *p = &device.pci; + device.api->pci_write16(p->bus, p->slot, p->function, 4, + device.original_command & ~4u); + } + device = (struct rtl_device){0}; +} + +const struct reliefos_driver_module r8169_driver_module = { + .magic = RELIEFOS_DRIVER_MODULE_MAGIC, + .abi_version = RELIEFOS_DRIVER_ABI_VERSION, + .struct_size = sizeof(struct reliefos_driver_module), + .kind = RELIEFOS_DRIVER_KIND_NETWORK, + .name = "r8169", .version = 1, .init = start, .fini = stop, +}; diff --git a/drivers/net/r8169/module.c b/drivers/net/r8169/module.c new file mode 100644 index 00000000..5e055a4f --- /dev/null +++ b/drivers/net/r8169/module.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#include + +extern const struct reliefos_driver_module r8169_driver_module; + +/** @brief Register the driver descriptor under the current native module owner. + * @return Zero including absent hardware, or a negative initialization errno. + */ +static int r8169_register(void) +{ + return driver_module_register(&r8169_driver_module, THIS_MODULE); +} + +/** @brief Finish module exit after the manager has drained callbacks and DMA. */ +static void r8169_exit(void) +{ +} + +module_init(r8169_register); +module_exit(r8169_exit); +MODULE_LICENSE("Apache-2.0 AND ISC AND BSD-4-Clause AND LicenseRef-Realtek-Firmware"); +MODULE_DESCRIPTION("ReliefNT Realtek RTL8111/8168 Gigabit and RTL8125 2.5GbE Ethernet"); +MODULE_ALIAS("pci:v000010ECd00008168sv*sd*bc*sc*i*"); +MODULE_ALIAS("pci:v000010ECd00008125sv*sd*bc*sc*i*"); diff --git a/drivers/net/r8169/rings.c b/drivers/net/r8169/rings.c new file mode 100644 index 00000000..4eaed4f5 --- /dev/null +++ b/drivers/net/r8169/rings.c @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +#include "internal.h" + +/** @brief Allocate coherent descriptor pages and fixed packet buffers. + * @param d Stopped device retaining each successful allocation for rollback. + * @return Zero or -ENOMEM; no allocation is freed until hardware STOP succeeds. + */ +int rtl_allocate_rings(struct rtl_device *d) +{ + d->rx_physical = d->api->alloc_dma(1, UINT64_MAX); + d->tx_physical = d->api->alloc_dma(1, UINT64_MAX); + d->rx_data_physical = d->api->alloc_dma(RTL_RX_PAGES, UINT64_MAX); + d->tx_data_physical = d->api->alloc_dma(RTL_TX_PAGES, UINT64_MAX); + if (!d->rx_physical || !d->tx_physical || !d->rx_data_physical || !d->tx_data_physical) + return -12; + d->rx = d->api->phys_to_virt(d->rx_physical); + d->tx = d->api->phys_to_virt(d->tx_physical); + d->rx_data = d->api->phys_to_virt(d->rx_data_physical); + d->tx_data = d->api->phys_to_virt(d->tx_data_physical); + if (!d->rx || !d->tx || !d->rx_data || !d->tx_data) + return -12; + for (unsigned i = 0; i < RTL_RX_COUNT; ++i) { + d->rx[i].address = d->rx_data_physical + (uint64_t)i * RTL_BUFFER_SIZE; + d->rx[i].options = 0; + d->rx[i].command = RTL_DESC_OWN | RTL_BUFFER_SIZE | + (i == RTL_RX_COUNT - 1 ? RTL_DESC_EOR : 0); + } + for (unsigned i = 0; i < RTL_TX_COUNT; ++i) { + d->tx[i].address = d->tx_data_physical + (uint64_t)i * RTL_BUFFER_SIZE; + d->tx[i].options = 0; + d->tx[i].command = i == RTL_TX_COUNT - 1 ? RTL_DESC_EOR : 0; + } + __atomic_thread_fence(__ATOMIC_RELEASE); + return 0; +} + +/** @brief Release coherent storage after hardware and PCI DMA admission stop. + * @param d Owned stopped device with drained callbacks, including partial allocation. + */ +void rtl_free_rings(struct rtl_device *d) +{ + if (d->rx_physical) + d->api->free_dma(d->rx_physical, 1); + if (d->tx_physical) + d->api->free_dma(d->tx_physical, 1); + if (d->rx_data_physical) + d->api->free_dma(d->rx_data_physical, RTL_RX_PAGES); + if (d->tx_data_physical) + d->api->free_dma(d->tx_data_physical, RTL_TX_PAGES); + d->rx_physical = d->tx_physical = d->rx_data_physical = d->tx_data_physical = 0; + d->rx = d->tx = NULL; + d->rx_data = d->tx_data = NULL; +} + +/** @brief Enqueue one Ethernet frame with ownership published after all bytes. + * @param d Pinned live device. @param frame Borrowed Ethernet bytes. + * @param length Frame size excluding FCS, up to RTL_MAX_FRAME. + * @return Zero, -EINVAL, -EMSGSIZE, -ENETDOWN or -EAGAIN for a full ring. + * IRQ-safe exclusion only protects the queue; this function never waits or allocates. + */ +int rtl_send(struct rtl_device *d, const void *frame, uint32_t length) +{ + if (!frame || length < 14) + return -22; + if (length > RTL_MAX_FRAME) + return -90; + if (!d->active || !(rtl_read8(d, 0x6c) & 2)) + return -100; + uint64_t flags; + kernel_spin_lock_irqsave(&d->tx_lock, &flags); + while (d->tx_clean != d->tx_next && !(d->tx[d->tx_clean].command & RTL_DESC_OWN)) { + __atomic_thread_fence(__ATOMIC_ACQUIRE); + d->tx_clean = (d->tx_clean + 1) % RTL_TX_COUNT; + } + unsigned index = d->tx_next; + unsigned next = (index + 1) % RTL_TX_COUNT; + if (next == d->tx_clean) { + kernel_spin_unlock_irqrestore(&d->tx_lock, flags); + return -11; + } + uint8_t *output = d->tx_data + index * RTL_BUFFER_SIZE; + const uint8_t *input = frame; + for (unsigned i = 0; i < length; ++i) + output[i] = input[i]; + /* Explicit zero padding avoids exposing previously transmitted packet bytes. */ + unsigned wire_length = length < 60 ? 60 : length; + for (unsigned i = length; i < wire_length; ++i) + output[i] = 0; + d->tx[index].options = 0; + __atomic_thread_fence(__ATOMIC_RELEASE); + d->tx[index].command = RTL_DESC_OWN | RTL_DESC_FIRST | RTL_DESC_LAST | wire_length | + (index == RTL_TX_COUNT - 1 ? RTL_DESC_EOR : 0); + __atomic_thread_fence(__ATOMIC_RELEASE); + d->tx_next = next; + if (d->family == RTL_FAMILY_8125) + rtl_write16(d, 0x90, 1); + else + rtl_write8(d, 0x38, 0x40); + (void)rtl_read8(d, 0x37); + kernel_spin_unlock_irqrestore(&d->tx_lock, flags); + return 0; +} + +/** @brief Copy a bounded complete frame and return its descriptor to hardware. + * @param d Pinned active device. @param frame Writable capacity-byte buffer. + * @param capacity Buffer capacity. @param length Optional size output, excluding FCS. + * @return One, zero for no completion, or negative errno; malformed chains are dropped. + * No allocation or hardware wait occurs while the IRQ-safe RX lock is held. + */ +int rtl_receive(struct rtl_device *d, void *frame, uint32_t capacity, uint32_t *length) +{ + if (length) + *length = 0; + if (!frame || !capacity) + return -22; + if (!d->active) + return -19; + uint64_t flags; + kernel_spin_lock_irqsave(&d->rx_lock, &flags); + unsigned index = d->rx_next; + uint32_t status = d->rx[index].command; + if (status & RTL_DESC_OWN) { + kernel_spin_unlock_irqrestore(&d->rx_lock, flags); + return 0; + } + __atomic_thread_fence(__ATOMIC_ACQUIRE); + uint32_t wire_length = status & 0x3fffu; + uint32_t bytes = wire_length >= 4 ? wire_length - 4 : 0; + uint32_t errors = RTL_RX_ERROR | (1u << 19) | (1u << 20) | (1u << 22); + int rc = 1; + if (wire_length > RTL_BUFFER_SIZE || bytes > RTL_MAX_FRAME || bytes > capacity) + rc = -90; + else if (wire_length < 18 || (status & errors) || d->dropping_fragments || + (status & (RTL_DESC_FIRST | RTL_DESC_LAST)) != (RTL_DESC_FIRST | RTL_DESC_LAST)) + rc = -74; + d->dropping_fragments = !(status & RTL_DESC_LAST); + if (rc == 1) { + const uint8_t *input = d->rx_data + index * RTL_BUFFER_SIZE; + uint8_t *output = frame; + for (unsigned i = 0; i < bytes; ++i) + output[i] = input[i]; + if (length) + *length = bytes; + } + d->rx[index].options = 0; + __atomic_thread_fence(__ATOMIC_RELEASE); + d->rx[index].command = RTL_DESC_OWN | RTL_BUFFER_SIZE | + (index == RTL_RX_COUNT - 1 ? RTL_DESC_EOR : 0); + d->rx_next = (index + 1) % RTL_RX_COUNT; + kernel_spin_unlock_irqrestore(&d->rx_lock, flags); + return rc; +} diff --git a/drivers/net/r8169/rtl8125.c b/drivers/net/r8169/rtl8125.c new file mode 100644 index 00000000..67457005 --- /dev/null +++ b/drivers/net/r8169/rtl8125.c @@ -0,0 +1,1086 @@ +/* $OpenBSD: if_rge.c,v 1.49 2026/11/05 07:54:52 kevlo Exp $ */ +/* + * Copyright (c) 2019, 2020, 2023-2026 + * Kevin Lo + * + * Copyright (c) 2019, 2020, 2025, 2026 + * Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#include "internal.h" +#include "rtl8125_regs.h" +#include "firmware_8125.h" +#include + +/* Private revision values are not shared with RTL8168. */ +enum { MAC_R25 = 1, MAC_R25B, MAC_R25D_1, MAC_R25D_2 }; +#define nitems(a) ((int)(sizeof(a) / sizeof((a)[0]))) +#define RGE_TYPE_R25D(d) ((d)->chip_revision == MAC_R25D_1 || (d)->chip_revision == MAC_R25D_2) +#define RGE_READ_1(d,r) ((d)->io_error ? 0 : rtl_read8((d),(r))) +#define RGE_READ_2(d,r) ((d)->io_error ? 0 : rtl_read16((d),(r))) +#define RGE_READ_4(d,r) ((d)->io_error ? 0 : rtl_read32((d),(r))) +#define RGE_WRITE_1(d,r,v) do { if (!(d)->io_error) rtl_write8((d),(r),(v)); } while (0) +#define RGE_WRITE_2(d,r,v) do { if (!(d)->io_error) rtl_write16((d),(r),(v)); } while (0) +#define RGE_WRITE_4(d,r,v) do { if (!(d)->io_error) rtl_write32((d),(r),(v)); } while (0) +#define RGE_SETBIT_1(d,r,m) RGE_WRITE_1((d),(r),RGE_READ_1((d),(r)) | (m)) +#define RGE_CLRBIT_1(d,r,m) RGE_WRITE_1((d),(r),RGE_READ_1((d),(r)) & ~(m)) +#define RGE_CLRBIT_2(d,r,m) RGE_WRITE_2((d),(r),RGE_READ_2((d),(r)) & ~(m)) +#define RGE_CLRBIT_4(d,r,m) RGE_WRITE_4((d),(r),RGE_READ_4((d),(r)) & ~(m)) +#define RGE_MAC_SETBIT(d,r,m) rge_mac_modify((d),(r),0,(m)) +#define RGE_MAC_CLRBIT(d,r,m) rge_mac_modify((d),(r),(m),0) +#define RGE_PHY_SETBIT(d,r,m) rge_phy_modify((d),(r),0,(m)) +#define RGE_PHY_CLRBIT(d,r,m) rge_phy_modify((d),(r),(m),0) +#define RGE_EPHY_SETBIT(d,r,m) rge_ephy_modify((d),(r),0,(m)) +#define RGE_EPHY_CLRBIT(d,r,m) rge_ephy_modify((d),(r),(m),0) + +/** @brief Poll a 32-bit handshake register without holding a lock. + * @param d Mapped controller. @param reg Handshake register offset. + * @param mask Bits to test. @param want Expected masked bits. + * @param ms Maximum number of millisecond sleeps. + * @return Register value, or zero with sticky -ETIMEDOUT/-ENODEV. + */ +static uint32_t rge_wait32(struct rtl_device *d, unsigned reg, uint32_t mask, + uint32_t want, unsigned ms) +{ + for (unsigned i = 0; !d->io_error; ++i) { + uint32_t v = rtl_read32(d, reg); + if (v == 0xffffffffu) { d->io_error = -ENODEV; break; } + if ((v & mask) == want) return v; + if (i == ms) { d->io_error = -ETIMEDOUT; break; } + rtl_delay_us(d, 1000); + } + return 0; +} + +/** @brief Access the direct MAC OCP window; no busy handshake is defined. + * @param sc Initialized controller. @param reg Even MAC OCP address. + * @param val Value written; no effect after a prior I/O failure. + */ +static void rge_write_mac_ocp(struct rtl_device *sc, uint16_t reg, uint16_t val) +{ + RGE_WRITE_4(sc, RGE_MACOCP, 0x80000000u | ((uint32_t)(reg >> 1) << 16) | val); +} +/** @brief Read one word through the direct MAC OCP window. + * @param sc Initialized controller. @param reg Even MAC OCP address. + * @return Register value, or zero after a prior I/O failure. + */ +static uint16_t rge_read_mac_ocp(struct rtl_device *sc, uint16_t reg) +{ + RGE_WRITE_4(sc, RGE_MACOCP, (uint32_t)(reg >> 1) << 16); + return (uint16_t)RGE_READ_4(sc, RGE_MACOCP); +} +/** @brief Change selected MAC OCP bits through the direct window. + * @param sc Initialized controller. @param reg Even MAC OCP address. + * @param clear Bits to clear. @param set Bits to set afterwards. + */ +static void rge_mac_modify(struct rtl_device *sc, uint16_t reg, uint16_t clear, uint16_t set) +{ + uint16_t v = rge_read_mac_ocp(sc, reg); + rge_write_mac_ocp(sc, reg, (v & ~clear) | set); +} +/** @brief Write PHY OCP and wait for hardware to clear its busy bit. + * @param sc Initialized controller. @param reg Even PHY OCP address. + * @param val Register value; a timeout is recorded in io_error. + */ +static void rge_write_phy_ocp(struct rtl_device *sc, uint16_t reg, uint16_t val) +{ + if (sc->io_error) return; + RGE_WRITE_4(sc, RGE_PHYOCP, 0x80000000u | ((uint32_t)(reg >> 1) << 16) | val); + rtl_delay_us(sc, 1); + (void)rge_wait32(sc, RGE_PHYOCP, 0x80000000u, 0, 20); +} +/** @brief Read PHY OCP and wait for hardware to set its ready bit. + * @param sc Initialized controller. @param reg Even PHY OCP address. + * @return Read value, or zero with sticky -ETIMEDOUT/-ENODEV. + */ +static uint16_t rge_read_phy_ocp(struct rtl_device *sc, uint16_t reg) +{ + if (sc->io_error) return 0; + RGE_WRITE_4(sc, RGE_PHYOCP, (uint32_t)(reg >> 1) << 16); + rtl_delay_us(sc, 1); + return (uint16_t)rge_wait32(sc, RGE_PHYOCP, 0x80000000u, 0x80000000u, 20); +} +/** @brief Change selected PHY OCP bits using bounded handshakes. + * @param sc Initialized controller. @param reg Even PHY OCP address. + * @param clear Bits to clear. @param set Bits to set afterwards. + */ +static void rge_phy_modify(struct rtl_device *sc, uint16_t reg, uint16_t clear, uint16_t set) +{ + uint16_t v = rge_read_phy_ocp(sc, reg); + rge_write_phy_ocp(sc, reg, (v & ~clear) | set); +} +/** @brief Write one EPHY register and wait for its busy handshake. + * @param sc Initialized controller. @param reg EPHY address. @param val Value to write. + */ +static void rge_write_ephy(struct rtl_device *sc, uint16_t reg, uint16_t val) +{ + if (sc->io_error) return; + RGE_WRITE_4(sc, RGE_EPHYAR, 0x80000000u | ((uint32_t)(reg & 0x7f) << 16) | val); + rtl_delay_us(sc, 1); + (void)rge_wait32(sc, RGE_EPHYAR, 0x80000000u, 0, 20); + if (!sc->io_error) rtl_delay_us(sc, 20); +} +/** @brief Read one EPHY register using the bounded ready handshake. + * @param sc Initialized controller. @param reg EPHY address. + * @return Read value, or zero with sticky timeout or removal error. + */ +static uint16_t rge_read_ephy(struct rtl_device *sc, uint16_t reg) +{ + if (sc->io_error) return 0; + RGE_WRITE_4(sc, RGE_EPHYAR, (uint32_t)(reg & 0x7f) << 16); + rtl_delay_us(sc, 1); + uint16_t v = (uint16_t)rge_wait32(sc, RGE_EPHYAR, 0x80000000u, 0x80000000u, 20); + if (!sc->io_error) rtl_delay_us(sc, 20); + return v; +} +/** @brief Change selected EPHY bits using bounded handshakes. + * @param sc Initialized controller. @param reg EPHY address. + * @param clear Bits to clear. @param set Bits to set afterwards. + */ +static void rge_ephy_modify(struct rtl_device *sc, uint16_t reg, uint16_t clear, uint16_t set) +{ + uint16_t v = rge_read_ephy(sc, reg); + rge_write_ephy(sc, reg, (v & ~clear) | set); +} +/** @brief Read an extended PCI configuration dword via the CSI window. + * @param sc Initialized controller. @param reg Aligned PCI configuration offset. + * @return Value, or zero with sticky timeout or removal error. + */ +static uint32_t rge_read_csi(struct rtl_device *sc, uint16_t reg) +{ + if (sc->io_error) return 0; + RGE_WRITE_4(sc, RGE_CSIAR, (reg & 0xfff) | 0xf000); + rtl_delay_us(sc, 1); + (void)rge_wait32(sc, RGE_CSIAR, 0x80000000u, 0x80000000u, 20); + if (!sc->io_error) rtl_delay_us(sc, 20); + return RGE_READ_4(sc, RGE_CSIDR); +} +/** @brief Write an extended PCI configuration dword via CSI. + * @param sc Initialized controller. @param reg Aligned PCI configuration offset. + * @param val Value written; sticky error prevents subsequent programming. + */ +static void rge_write_csi(struct rtl_device *sc, uint16_t reg, uint32_t val) +{ + if (sc->io_error) return; + RGE_WRITE_4(sc, RGE_CSIDR, val); + RGE_WRITE_4(sc, RGE_CSIAR, 0x80000000u | 0xf000 | (reg & 0xfff)); + rtl_delay_us(sc, 1); + (void)rge_wait32(sc, RGE_CSIAR, 0x80000000u, 0, 20); + if (!sc->io_error) rtl_delay_us(sc, 20); +} +/** @brief Read a standard MII register via its PHY OCP address. + * @param sc Initialized controller. @param reg Clause 22 register number. + * @return MII value, or zero with sticky error. + */ +static uint16_t rge_mii_read(struct rtl_device *sc, unsigned reg) +{ + return rge_read_phy_ocp(sc, (uint16_t)(0xa400 + reg * 2)); +} +/** @brief Write a standard MII register via its PHY OCP address. + * @param sc Initialized controller. @param reg Clause 22 register number. + * @param val Register value. + */ +static void rge_mii_write(struct rtl_device *sc, unsigned reg, uint16_t val) +{ + rge_write_phy_ocp(sc, (uint16_t)(0xa400 + reg * 2), val); +} +/** @brief Enter or leave the PHY patch mode and verify its acknowledgement. + * @param sc Initialized controller. @param set Nonzero to enter patch mode. + */ +static void rge_patch_phy_mcu(struct rtl_device *sc, int set) +{ + if (set) RGE_PHY_SETBIT(sc, 0xb820, 0x0010); + else RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = rge_read_phy_ocp(sc, 0xb800); + if (sc->io_error) return; + if (!!(v & 0x0040) == !!set) return; + if (i == 100) { sc->io_error = -ETIMEDOUT; return; } + rtl_delay_us(sc, 1000); + } +} + +/** @brief Load the revision-matched PHY program and verify its version marker. + * @param sc Initialized controller. @param rcodever Expected Realtek program version. + */ +static void rge_phy_config_mcu(struct rtl_device *sc, uint16_t rcodever) +{ + const struct rtl8125_fw_pair *p; + unsigned count; + switch (sc->chip_revision) { + case MAC_R25: p = mac_r25_mcu; count = nitems(mac_r25_mcu); break; + case MAC_R25B: p = mac_r25b_mcu; count = nitems(mac_r25b_mcu); break; + case MAC_R25D_1: p = mac_r25d_1_mcu; count = nitems(mac_r25d_1_mcu); break; + case MAC_R25D_2: p = mac_r25d_2_mcu; count = nitems(mac_r25d_2_mcu); break; + default: sc->io_error = -ENODEV; return; + } + rge_write_phy_ocp(sc, 0xa436, 0x801e); + uint16_t old = rge_read_phy_ocp(sc, 0xa438); + if (sc->io_error || old == rcodever) return; + rge_patch_phy_mcu(sc, 1); + if (sc->chip_revision == MAC_R25) { + rge_write_phy_ocp(sc, 0xa436, 0x8024); + rge_write_phy_ocp(sc, 0xa438, 0x8601); + rge_write_phy_ocp(sc, 0xa436, 0xb82e); + rge_write_phy_ocp(sc, 0xa438, 0x0001); + RGE_PHY_SETBIT(sc, 0xb820, 0x0080); + } + for (unsigned i = 0; i < count && !sc->io_error; ++i) { + if ((sc->chip_revision == MAC_R25D_1 && (i == 2403 || i == 2528)) || + (sc->chip_revision == MAC_R25D_2 && i == 1269)) { + rge_patch_phy_mcu(sc, 0); + rge_patch_phy_mcu(sc, 1); + } + rge_write_phy_ocp(sc, p[i].reg, p[i].val); + } + if (sc->chip_revision == MAC_R25) { + RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); + rge_write_phy_ocp(sc, 0xa436, 0); + rge_write_phy_ocp(sc, 0xa438, 0); + RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); + rge_write_phy_ocp(sc, 0xa436, 0x8024); + rge_write_phy_ocp(sc, 0xa438, 0); + } + rge_patch_phy_mcu(sc, 0); + rge_write_phy_ocp(sc, 0xa436, 0x801e); + rge_write_phy_ocp(sc, 0xa438, rcodever); + rge_write_phy_ocp(sc, 0xa436, 0x801e); + uint16_t now = rge_read_phy_ocp(sc, 0xa438); + if (!sc->io_error && now != rcodever) sc->io_error = -EIO; +} + +/** @brief Apply the revision-specific Realtek PHY tuning sequence. + * @param sc Mapped controller; io_error suppresses programming after any failure. + */ +static void +rge_phy_config_mac_r25(struct rtl_device *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg3_a438_value[] = + { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff, + 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; + + static const uint16_t mac_cfg3_b88e_value[] = + { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, + 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, + 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, + 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, + 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050, + 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 }; + + rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); + val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); + val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; + rge_write_phy_ocp(sc, 0xad32, val | 0x0006); + RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); + RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); + val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; + rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; + rge_write_phy_ocp(sc, 0xad40, val | 0x0040); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; + rge_write_phy_ocp(sc, 0xad40, val | 0x0004); + RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); + RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); + val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; + rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); + rge_write_phy_ocp(sc, 0xad4c, 0x00a8); + rge_write_phy_ocp(sc, 0xac5c, 0x01ff); + val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); + rge_write_phy_ocp(sc, 0xb87c, 0x8157); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + rge_write_phy_ocp(sc, 0xb87c, 0x8159); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x80a2); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + rge_write_phy_ocp(sc, 0xb87c, 0x809c); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + + rge_write_phy_ocp(sc, 0xa436, 0x81b3); + for (i = 0; i < nitems(mac_cfg3_a438_value); i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); + for (i = 0; i < 26; i++) + rge_write_phy_ocp(sc, 0xa438, 0); + rge_write_phy_ocp(sc, 0xa436, 0x8257); + rge_write_phy_ocp(sc, 0xa438, 0x020f); + rge_write_phy_ocp(sc, 0xa436, 0x80ea); + rge_write_phy_ocp(sc, 0xa438, 0x7843); + + rge_patch_phy_mcu(sc, 1); + RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); + RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); + for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) { + rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); + rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); + } + RGE_PHY_SETBIT(sc, 0xb896, 0x0001); + rge_patch_phy_mcu(sc, 0); + + RGE_PHY_SETBIT(sc, 0xd068, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81a2); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; + rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); + RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); + RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + RGE_PHY_SETBIT(sc, 0xa424, 0x0008); +} + +/** @brief Apply the revision-specific Realtek PHY tuning sequence. + * @param sc Mapped controller; io_error suppresses programming after any failure. + */ +static void +rge_phy_config_mac_r25b(struct rtl_device *sc) +{ + uint16_t val; + int i; + + rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac46, val | 0x0090); + val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; + rge_write_phy_ocp(sc, 0xad30, val | 0x0001); + rge_write_phy_ocp(sc, 0xb87c, 0x80f5); + rge_write_phy_ocp(sc, 0xb87e, 0x760e); + rge_write_phy_ocp(sc, 0xb87c, 0x8107); + rge_write_phy_ocp(sc, 0xb87e, 0x360e); + rge_write_phy_ocp(sc, 0xb87c, 0x8551); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); + val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; + rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); + for (i = 0; i < 10; i++) { + rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); + rge_write_phy_ocp(sc, 0xa438, 0x2417); + } + RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); + val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); + rge_write_phy_ocp(sc, 0xa436, 0x8170); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; + rge_write_phy_ocp(sc, 0xa438, val | 0xd800); + RGE_PHY_SETBIT(sc, 0xa424, 0x0008); +} + +/** @brief Apply the revision-specific Realtek PHY tuning sequence. + * @param sc Mapped controller; io_error suppresses programming after any failure. + */ +static void +rge_phy_config_mac_r25d_1(struct rtl_device *sc) +{ + uint16_t val; + int i; + + rge_phy_config_mcu(sc, RGE_MAC_R25D_1_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + + rge_patch_phy_mcu(sc, 1); + RGE_PHY_SETBIT(sc, 0xbf96, 0x8000); + val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007; + rge_write_phy_ocp(sc, 0xbf94, val | 0x0005); + val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00; + rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); + RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); + RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); + val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; + rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); + RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100); + RGE_PHY_SETBIT(sc, 0xa466, 0x0002); + rge_write_phy_ocp(sc, 0xa436, 0x836a); + RGE_PHY_CLRBIT(sc, 0xa438, 0xff00); + rge_patch_phy_mcu(sc, 0); + + rge_write_phy_ocp(sc, 0xb87c, 0x832c); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700; + rge_write_phy_ocp(sc, 0xb106, val | 0x0100); + val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700; + rge_write_phy_ocp(sc, 0xb206, val | 0x0200); + val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700; + rge_write_phy_ocp(sc, 0xb306, val | 0x0300); + rge_write_phy_ocp(sc, 0xb87c, 0x80cb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0300); + rge_write_phy_ocp(sc, 0xbcf4, 0x0000); + rge_write_phy_ocp(sc, 0xbcf6, 0x0000); + rge_write_phy_ocp(sc, 0xbc12, 0x0000); + rge_write_phy_ocp(sc, 0xb87c, 0x844d); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); + + rge_write_phy_ocp(sc, 0xb87c, 0x8feb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0600); + + val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; + rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4); + rge_write_phy_ocp(sc, 0xb87c, 0x8105); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8117); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8103); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); + rge_write_phy_ocp(sc, 0xb87c, 0x8115); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); + RGE_PHY_CLRBIT(sc, 0xad40, 0x0030); + val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f; + rge_write_phy_ocp(sc, 0xad66, val | 0x0007); + val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000; + rge_write_phy_ocp(sc, 0xad68, val | 0x8000); + val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00; + rge_write_phy_ocp(sc, 0xad68, val | 0x0500); + val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f; + rge_write_phy_ocp(sc, 0xad68, val | 0x0002); + val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000; + rge_write_phy_ocp(sc, 0xad6a, val | 0x7000); + rge_write_phy_ocp(sc, 0xac50, 0x01e8); + rge_write_phy_ocp(sc, 0xa436, 0x81fa); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5400); + val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0; + rge_write_phy_ocp(sc, 0xa864, val | 0x00c0); + val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff; + rge_write_phy_ocp(sc, 0xa42c, val | 0x0002); + rge_write_phy_ocp(sc, 0xa436, 0x80e1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); + rge_write_phy_ocp(sc, 0xa436, 0x80de); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000; + rge_write_phy_ocp(sc, 0xa438, val | 0x0700); + RGE_PHY_SETBIT(sc, 0xa846, 0x0080); + rge_write_phy_ocp(sc, 0xa436, 0x80ba); + rge_write_phy_ocp(sc, 0xa438, 0x8a04); + rge_write_phy_ocp(sc, 0xa436, 0x80bd); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xca00); + rge_write_phy_ocp(sc, 0xa436, 0x80b7); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xb300); + rge_write_phy_ocp(sc, 0xa436, 0x80ce); + rge_write_phy_ocp(sc, 0xa438, 0x8a04); + rge_write_phy_ocp(sc, 0xa436, 0x80d1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xca00); + rge_write_phy_ocp(sc, 0xa436, 0x80cb); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xbb00); + rge_write_phy_ocp(sc, 0xa436, 0x80a6); + rge_write_phy_ocp(sc, 0xa438, 0x4909); + rge_write_phy_ocp(sc, 0xa436, 0x80a8); + rge_write_phy_ocp(sc, 0xa438, 0x05b8); + rge_write_phy_ocp(sc, 0xa436, 0x8200); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5800); + rge_write_phy_ocp(sc, 0xa436, 0x8ff1); + rge_write_phy_ocp(sc, 0xa438, 0x7078); + rge_write_phy_ocp(sc, 0xa436, 0x8ff3); + rge_write_phy_ocp(sc, 0xa438, 0x5d78); + rge_write_phy_ocp(sc, 0xa436, 0x8ff5); + rge_write_phy_ocp(sc, 0xa438, 0x7862); + rge_write_phy_ocp(sc, 0xa436, 0x8ff7); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1400); + + rge_write_phy_ocp(sc, 0xa436, 0x814c); + rge_write_phy_ocp(sc, 0xa438, 0x8455); + rge_write_phy_ocp(sc, 0xa436, 0x814e); + rge_write_phy_ocp(sc, 0xa438, 0x84a6); + rge_write_phy_ocp(sc, 0xa436, 0x8163); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0600); + rge_write_phy_ocp(sc, 0xa436, 0x816a); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0500); + rge_write_phy_ocp(sc, 0xa436, 0x8171); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1f00); + + val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f; + rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006); + for (i = 0; i < 10; i++) { + rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3); + RGE_PHY_CLRBIT(sc, 0xa438, 0x0700); + } + val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70; + rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500); + rge_write_phy_ocp(sc, 0xbfa2, 0x9d00); + rge_write_phy_ocp(sc, 0xa436, 0x8165); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; + rge_write_phy_ocp(sc, 0xa438, val | 0x0200); + + rge_write_phy_ocp(sc, 0xa436, 0x8019); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + rge_write_phy_ocp(sc, 0xa436, 0x8fe3); + rge_write_phy_ocp(sc, 0xa438, 0x0005); + rge_write_phy_ocp(sc, 0xa438, 0x0000); + rge_write_phy_ocp(sc, 0xa438, 0x00ed); + rge_write_phy_ocp(sc, 0xa438, 0x0502); + rge_write_phy_ocp(sc, 0xa438, 0x0b00); + rge_write_phy_ocp(sc, 0xa438, 0xd401); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x2900); + + rge_write_phy_ocp(sc, 0xa436, 0x8018); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1700); + + rge_write_phy_ocp(sc, 0xa436, 0x815b); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1700); + + RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000); + RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); + RGE_PHY_SETBIT(sc, 0xa430, 0x1001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0080); +} + +/** @brief Apply the revision-specific Realtek PHY tuning sequence. + * @param sc Mapped controller; io_error suppresses programming after any failure. + */ +static void +rge_phy_config_mac_r25d_2(struct rtl_device *sc) +{ + uint16_t val; + + rge_phy_config_mcu(sc, RGE_MAC_R25D_2_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + + rge_patch_phy_mcu(sc, 1); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); + RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); + RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); + val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; + rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); + RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + rge_patch_phy_mcu(sc, 0); + + val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; + rge_write_phy_ocp(sc, 0xac7e, val | 0x00b4); + rge_write_phy_ocp(sc, 0xb87c, 0x8105); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8117); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8103); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); + rge_write_phy_ocp(sc, 0xb87c, 0x8115); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); + rge_write_phy_ocp(sc, 0xb87c, 0x8feb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + rge_write_phy_ocp(sc, 0xb87c, 0x8fea); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x80d6); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xef00); + RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); + RGE_PHY_CLRBIT(sc, 0xa448, 0x0400); + RGE_PHY_CLRBIT(sc, 0xa586, 0x0400); + RGE_PHY_SETBIT(sc, 0xa430, 0x1001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0080); +} + +/* EPHY tuning is from the ISC-licensed if_rgereg.h reference. */ +static const struct rtl8125_fw_pair mac_r25_ephy[] = { + {0x0004,0xd000},{0x000a,0x8653},{0x0023,0xab66},{0x0020,0x9455}, + {0x0021,0x99ff},{0x0029,0xfe04},{0x0044,0xd000},{0x004a,0x8653}, + {0x0063,0xab66},{0x0060,0x9455},{0x0061,0x99ff},{0x0069,0xfe04} +}; +static const struct rtl8125_fw_pair mac_r25b_ephy[] = { + {0x000b,0xa908},{0x001e,0x20eb},{0x0022,0x0023},{0x0002,0x60c2}, + {0x0029,0xff00},{0x004b,0xa908},{0x005e,0x20eb},{0x0062,0x0023}, + {0x0042,0x60c2},{0x0069,0xff00} +}; + +/** @brief Tune the revision-specific PCIe analog PHY. + * @param sc Mapped controller; each access propagates a bounded handshake error. + */ +static void rge_ephy_config(struct rtl_device *sc) +{ + if (sc->chip_revision == MAC_R25) { + for (int i = 0; i < nitems(mac_r25_ephy) && !sc->io_error; ++i) + rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val); + uint16_t v = rge_read_ephy(sc, 0x002a) & ~0x7000; + rge_write_ephy(sc, 0x002a, v | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); + RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); + rge_write_ephy(sc, 0x0002, 0x6042); + rge_write_ephy(sc, 0x0006, 0x0014); + v = rge_read_ephy(sc, 0x006a) & ~0x7000; + rge_write_ephy(sc, 0x006a, v | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); + RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); + rge_write_ephy(sc, 0x0042, 0x6042); + rge_write_ephy(sc, 0x0046, 0x0014); + } else if (sc->chip_revision == MAC_R25B) { + for (int i = 0; i < nitems(mac_r25b_ephy) && !sc->io_error; ++i) + rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val); + } +} + +/** @brief Change the MAC MCU RAM page while initialization owns the OCP window. + * @param sc Mapped controller. @param page Page number from zero through two. + */ +static void rge_switch_mcu_ram_page(struct rtl_device *sc, unsigned page) +{ + rge_mac_modify(sc, 0xe446, 0x0003, (uint16_t)page); +} +/** @brief Load the MAC microcode appropriate to this silicon revision. + * @param sc Identified controller with MAC MCU disabled. + */ +static void rge_mac_config_mcu(struct rtl_device *sc) +{ + const struct rtl8125_fw_pair *p = 0; + unsigned count = 0; + if (sc->chip_revision == MAC_R25) { + p = rtl8125_mac_bps; count = nitems(rtl8125_mac_bps); + } else if (sc->chip_revision == MAC_R25B) { + p = rtl8125b_mac_bps; count = nitems(rtl8125b_mac_bps); + } else if (sc->chip_revision == MAC_R25D_2) { + p = rtl8125d_2_mac_bps; count = nitems(rtl8125d_2_mac_bps); + } + if (sc->chip_revision == MAC_R25B) { + rge_switch_mcu_ram_page(sc, 0); + for (unsigned i = 0; i < count && !sc->io_error; ++i) + rge_write_mac_ocp(sc, p[i].reg, p[i].val); + return; + } + for (unsigned page = 0; page < 3 && !sc->io_error; ++page) { + rge_switch_mcu_ram_page(sc, page); + if (sc->chip_revision == MAC_R25D_1) { + static const uint16_t init[] = {0xe002,0xe006,0x4166,0x9cf6, + 0xc002,0xb800,0x14a4,0xc102,0xb900}; + for (unsigned i = 0; i < sizeof(init)/sizeof(init[0]); ++i) + rge_write_mac_ocp(sc, 0xf800 + i * 2, page == 0 ? init[i] : 0); + for (unsigned reg = 0xf812; reg <= 0xf9f6; reg += 2) + rge_write_mac_ocp(sc, reg, 0); + } else { + for (unsigned i = 0; i < count && !sc->io_error; ++i) { + if (sc->chip_revision == MAC_R25 && page == 2 && p[i].reg >= 0xf9f8) + continue; + rge_write_mac_ocp(sc, p[i].reg, page == 0 ? p[i].val : 0); + } + if (sc->chip_revision == MAC_R25D_2) + for (unsigned reg = 0xf884; reg <= 0xf9f6; reg += 2) + rge_write_mac_ocp(sc, reg, 0); + } + if (sc->chip_revision == MAC_R25) { + if (page == 2) { + rge_write_mac_ocp(sc, 0xf9f8, 0x6486); + rge_write_mac_ocp(sc, 0xf9fa, 0x0b15); + rge_write_mac_ocp(sc, 0xf9fc, 0x090e); + rge_write_mac_ocp(sc, 0xf9fe, 0x1139); + } + } else { + rge_write_mac_ocp(sc, 0xf9f8, page == 2 ? 0x6938 : 0); + rge_write_mac_ocp(sc, 0xf9fa, page == 2 ? (sc->chip_revision == MAC_R25D_1 ? 0x0a18 : 0x0a19) : 0); + rge_write_mac_ocp(sc, 0xf9fc, page == 2 ? (sc->chip_revision == MAC_R25D_1 ? 0x0217 : 0x030e) : 0); + rge_write_mac_ocp(sc, 0xf9fe, page == 2 ? (sc->chip_revision == MAC_R25D_1 ? 0x0d2a : 0x0b2f) : 0); + } + } + rge_write_mac_ocp(sc, 0xfc26, 0x8000); + if (sc->chip_revision == MAC_R25) { + rge_write_mac_ocp(sc, 0xfc2a, 0x0540); + rge_write_mac_ocp(sc, 0xfc2e, 0x0a06); + rge_write_mac_ocp(sc, 0xfc30, 0x0eb8); + rge_write_mac_ocp(sc, 0xfc32, 0x3a5c); + rge_write_mac_ocp(sc, 0xfc34, 0x10a8); + rge_write_mac_ocp(sc, 0xfc40, 0x0d54); + rge_write_mac_ocp(sc, 0xfc42, 0x0e24); + rge_write_mac_ocp(sc, 0xfc48, 0x307a); + } else { + rge_write_mac_ocp(sc, 0xfc28, sc->chip_revision == MAC_R25D_1 ? 0x14a2 : 0x2382); + rge_write_mac_ocp(sc, 0xfc48, 0x0001); + } +} +/** @brief Disable controller clock request and PME state with configuration unlocked. + * @param sc Mapped controller; the original configuration lock state is preserved. + */ +static void rge_disable_aspm_clkreq(struct rtl_device *sc) +{ + bool unlock = (RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) != RGE_EECMD_WRITECFG; + if (unlock) RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); + if (unlock) RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); +} +/** @brief Request RX/TX shutdown, confirm both FIFO conditions, and reset the MAC. + * @param sc Mapped controller, without a lock held or competing callbacks. + * @return Zero on completed reset, or sticky negative timeout/removal errno. + */ +static int rge_reset(struct rtl_device *sc) +{ + RGE_WRITE_4(sc, RGE_IMR, 0); + RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + RGE_WRITE_4(sc, RGE_TIMERINT1, 0); + RGE_WRITE_4(sc, RGE_TIMERINT2, 0); + RGE_WRITE_4(sc, RGE_TIMERINT3, 0); + RGE_CLRBIT_4(sc, RGE_RXCFG, 0x3f); + RGE_SETBIT_1(sc, RGE_PPSW, 0x08); + RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ); + if (!sc->io_error) rtl_delay_us(sc, 200); + for (unsigned i = 0; !sc->io_error; ++i) { + uint8_t v = RGE_READ_1(sc, RGE_MCUCMD); + if (v == 0xff) { sc->io_error = -ENODEV; break; } + if ((v & 0x30) == 0x30) break; + if (i == 150) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + if (sc->chip_revision != MAC_R25) { + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = RGE_READ_2(sc, RGE_IM); + if (v == 0xffff) { sc->io_error = -ENODEV; break; } + if ((v & 0x0103) == 0x0103) break; + if (i == 150) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + } + /* Keep both engines disabled after FIFO drain while issuing reset. */ + RGE_WRITE_1(sc, RGE_CMD, 0); + RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); + for (unsigned i = 0; !sc->io_error; ++i) { + uint8_t v = RGE_READ_1(sc, RGE_CMD); + if (v == 0xff) { sc->io_error = -ENODEV; break; } + if (!(v & (RGE_CMD_RESET | RGE_CMD_RXENB | RGE_CMD_TXENB))) break; + if (i == 100) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + return sc->io_error; +} + +/** @brief Exit out-of-band mode before changing MAC and PHY configuration. + * @param sc Mapped and identified controller with exclusive initialization access. + * @return Zero, or the first negative hardware error. + */ +static int rge_exit_oob(struct rtl_device *sc) +{ + rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); + if (rge_reset(sc)) return sc->io_error; + RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); + RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); + for (unsigned stage = 0; stage < 2 && !sc->io_error; ++stage) { + if (stage) { + rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); + rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); + rge_write_mac_ocp(sc, 0xc01e, 0x5555); + } + if (!sc->io_error) rtl_delay_us(sc, 100); + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = RGE_READ_2(sc, RGE_TWICMD); + if (v == 0xffff) { sc->io_error = -ENODEV; break; } + if (v & 0x0200) break; + if (i == 10) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + } + if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = rge_read_phy_ocp(sc, 0xa420); + if (sc->io_error) break; + if ((v & 7) == 2) break; + if (i == 1000) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100); + if (sc->chip_revision != MAC_R25) RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); + } + return sc->io_error; +} +/** @brief Power the PHY and load the matching controller microcode. + * @param sc Identified controller, in exclusive task context. + * @return Zero or a negative error from a power, CSI, patch, or reset handshake. + */ +static int rge_chipinit(struct rtl_device *sc) +{ + if (rge_exit_oob(sc)) return sc->io_error; + RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); + rge_mii_write(sc, 0, 0x1000); + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = rge_read_phy_ocp(sc, 0xa420); + if (sc->io_error) break; + if ((v & 7) == 3) break; + if (i == 1000) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + rge_disable_aspm_clkreq(sc); + RGE_CLRBIT_1(sc, 0xf1, 0x80); + RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); + rge_disable_aspm_clkreq(sc); + rge_write_mac_ocp(sc, 0xfc48, 0); + for (unsigned reg = 0xfc28; reg < 0xfc48 && !sc->io_error; reg += 2) + rge_write_mac_ocp(sc, reg, 0); + if (!sc->io_error) rtl_delay_us(sc, 3000); + rge_write_mac_ocp(sc, 0xfc26, 0); + rge_mac_config_mcu(sc); + if (sc->chip_revision == MAC_R25 && rge_read_phy_ocp(sc, 0xc416) != 0x0500) { + rge_patch_phy_mcu(sc, 1); + rge_write_phy_ocp(sc, 0xc416, 0); + rge_write_phy_ocp(sc, 0xc416, 0x0500); + rge_patch_phy_mcu(sc, 0); + } + uint32_t status = rge_read_csi(sc, 0x108); + rge_write_csi(sc, 0x108, status | 0x00100000); + if (!sc->io_error) (void)rge_reset(sc); + return sc->io_error; +} +/** @brief Reset, patch, and tune the Ethernet PHY and disable EEE. + * @param sc Identified powered controller with matching firmware data. + * @return Zero or the first negative programming or timeout error. + */ +static int rge_phy_config(struct rtl_device *sc) +{ + rge_ephy_config(sc); + rge_mii_write(sc, 4, rge_mii_read(sc, 4) & ~0x01e0); + rge_mii_write(sc, 9, rge_mii_read(sc, 9) & ~0x0300); + RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX); + rge_mii_write(sc, 0, 0x9200); + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t v = rge_mii_read(sc, 0); + if (sc->io_error) break; + if (!(v & 0x8000)) break; + if (i == 2500) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + if (sc->io_error) return sc->io_error; + switch (sc->chip_revision) { + case MAC_R25: rge_phy_config_mac_r25(sc); break; + case MAC_R25B: rge_phy_config_mac_r25b(sc); break; + case MAC_R25D_1: rge_phy_config_mac_r25d_1(sc); break; + case MAC_R25D_2: rge_phy_config_mac_r25d_2(sc); break; + default: sc->io_error = -ENODEV; return sc->io_error; + } + RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); + RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); + if (sc->chip_revision == MAC_R25) { + RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); + RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); + } else RGE_PHY_SETBIT(sc, 0xa432, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006); + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); + RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); + RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); + RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); + return sc->io_error; +} +/** @brief Advertise ordinary 10/100/1000/2500BASE-T and restart negotiation. + * @param sc Patched controller with its PHY accessible. + * @return Zero or the first negative PHY error or reset timeout. + */ +static int rge_autoneg(struct rtl_device *sc) +{ + RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); + RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); + uint16_t v = rge_read_phy_ocp(sc, 0xa5d4) | RGE_ADV_2500TFDX; + rge_mii_write(sc, 4, 0x0de1); /* selector, 10/100 half/full and pause */ + rge_mii_write(sc, 9, 0x0300); /* 1000BASE-T half/full */ + rge_write_phy_ocp(sc, 0xa5d4, v); + rge_mii_write(sc, 0, 0x9200); + for (unsigned i = 0; !sc->io_error; ++i) { + uint16_t control = rge_mii_read(sc, 0); + if (sc->io_error) break; + if (!(control & 0x8000)) break; + if (i == 2500) { sc->io_error = -ETIMEDOUT; break; } + rtl_delay_us(sc, 1000); + } + return sc->io_error; +} + +/** @brief Identify a supported RTL8125 MAC using TxConfig's hardware revision. + * @param d Mapped device with xid set before reset. + * @return Zero with chip metadata, or -ENODEV for unsupported silicon. + */ +int rtl8125_identify(struct rtl_device *d) +{ + switch (d->xid & 0x7cf00000u) { + case 0x60900000u: d->chip_revision = MAC_R25; d->chip_name = "RTL8125A"; break; + case 0x64100000u: d->chip_revision = MAC_R25B; d->chip_name = "RTL8125B"; break; + case 0x68800000u: d->chip_revision = MAC_R25D_1; d->chip_name = "RTL8125D-1"; break; + case 0x68900000u: d->chip_revision = MAC_R25D_2; d->chip_name = "RTL8125D-2"; break; + default: return -ENODEV; + } + return 0; +} +/** @brief Load the matching firmware and configure one standard RX/TX queue. + * @param d Identified mapped device with rings and PCI bus mastering enabled. + * @return Zero with RX/TX running, or negative errno retaining all resources. + */ +int rtl8125_start(struct rtl_device *d) +{ + if (d->io_error) return d->io_error; + if (!d->registers || d->mmio_bytes < 0x604a || !d->rx || !d->tx || + (d->rx_physical & 0xff) || (d->tx_physical & 0xff)) return -EINVAL; + if (rge_chipinit(d) || rge_phy_config(d)) return d->io_error; + + RGE_SETBIT_1(d, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_WRITE_4(d, RGE_MAC0, (uint32_t)d->mac[0] | (uint32_t)d->mac[1] << 8 | + (uint32_t)d->mac[2] << 16 | (uint32_t)d->mac[3] << 24); + RGE_WRITE_4(d, RGE_MAC4, (uint32_t)d->mac[4] | (uint32_t)d->mac[5] << 8); + RGE_CLRBIT_1(d, 0xf1, 0x80); + rge_disable_aspm_clkreq(d); + RGE_WRITE_2(d, RGE_EEE_TXIDLE_TIMER, 16408); + RGE_WRITE_4(d, RGE_RXDESC_ADDR_LO, (uint32_t)d->rx_physical); + RGE_WRITE_4(d, RGE_RXDESC_ADDR_HI, (uint32_t)(d->rx_physical >> 32)); + RGE_WRITE_4(d, RGE_TXDESC_ADDR_LO, (uint32_t)d->tx_physical); + RGE_WRITE_4(d, RGE_TXDESC_ADDR_HI, (uint32_t)(d->tx_physical >> 32)); + + /* Bit 24 selects the extended 32-byte RX descriptor, so leave it clear. */ + uint32_t rxconf = d->chip_revision == MAC_R25 ? 0x40000700u : + d->chip_revision == MAC_R25B ? 0x40000c00u : 0x40200c00u; + RGE_WRITE_4(d, RGE_RXCFG, rxconf); + RGE_WRITE_4(d, RGE_TXCFG, 0x03000700); + uint32_t cfg = rge_read_csi(d, 0x70c); + rge_write_csi(d, 0x70c, (cfg & ~0x3f000000u) | 0x27000000u); + if (!RGE_TYPE_R25D(d)) RGE_WRITE_2(d, 0x0382, 0x221b); + RGE_WRITE_4(d, RGE_RSS_CTRL, 0); + RGE_CLRBIT_2(d, RGE_RXQUEUE_CTRL, 0x001c); + RGE_CLRBIT_1(d, RGE_CFG1, RGE_CFG1_SPEED_DOWN); + rge_write_mac_ocp(d, 0xc140, 0xffff); + rge_write_mac_ocp(d, 0xc142, 0xffff); + /* Bit 0 selects the extended TX layout; shared rings have 16-byte entries. */ + RGE_MAC_CLRBIT(d, 0xeb58, 0x0001); + rge_mac_modify(d, 0xe614, 0x0700, d->chip_revision == MAC_R25B ? 0x0200 : 0x0300); + rge_mac_modify(d, 0xe63e, 0x0c30, 0x0020); + RGE_MAC_CLRBIT(d, 0xc0b4, 0x0001); + RGE_MAC_SETBIT(d, 0xc0b4, 0x0001); + RGE_MAC_SETBIT(d, 0xc0b4, 0x000c); + rge_mac_modify(d, 0xeb6a, 0x00ff, 0x0033); + rge_mac_modify(d, 0xeb50, 0x03e0, 0x0040); + RGE_MAC_CLRBIT(d, 0xe056, 0x00f0); + RGE_WRITE_1(d, RGE_TDFNR, 0x10); + RGE_MAC_CLRBIT(d, 0xe040, 0x1000); + rge_mac_modify(d, 0xea1c, 0x0003, 0x0001); + rge_write_mac_ocp(d, 0xe0c0, RGE_TYPE_R25D(d) ? 0x4403 : 0x4000); + RGE_MAC_SETBIT(d, 0xe052, 0x0060); + RGE_MAC_CLRBIT(d, 0xe052, 0x0088); + rge_mac_modify(d, 0xd430, 0x0fff, 0x045f); + RGE_SETBIT_1(d, RGE_DLLPR, 0xc0); + RGE_SETBIT_1(d, RGE_PPSW, 0x40); + if (d->chip_revision == MAC_R25) RGE_SETBIT_1(d, RGE_MCUCMD, 0x01); + if (!RGE_TYPE_R25D(d)) RGE_MAC_CLRBIT(d, 0xe080, 0x0002); + RGE_MAC_CLRBIT(d, 0xea1c, 0x0004); + RGE_MAC_SETBIT(d, 0xeb54, 0x0001); + if (!d->io_error) rtl_delay_us(d, 1); + RGE_MAC_CLRBIT(d, 0xeb54, 0x0001); + RGE_CLRBIT_2(d, 0x1880, 0x0030); + if (d->chip_revision != MAC_R25) RGE_CLRBIT_1(d, RGE_INT_CFG0, 0x01); + RGE_WRITE_4(d, RGE_TIMERINT0, 0); + RGE_WRITE_4(d, RGE_TIMERINT1, 0); + RGE_WRITE_4(d, RGE_TIMERINT2, 0); + RGE_WRITE_4(d, RGE_TIMERINT3, 0); + for (unsigned i = 0; i < (d->chip_revision == MAC_R25B ? 32u : 64u) && !d->io_error; ++i) + RGE_WRITE_4(d, RGE_INTMITI(i), 0); + RGE_MAC_SETBIT(d, 0xc0ac, 0x1f80); + rge_write_mac_ocp(d, 0xe098, 0xc302); + RGE_MAC_CLRBIT(d, 0xe032, 0x0003); + cfg = rge_read_csi(d, 0x98); + rge_write_csi(d, 0x98, cfg & ~0x0000ff00u); + if (!d->io_error) rtl_delay_us(d, 20); + rge_mac_modify(d, 0xe092, 0x00ff, RGE_TYPE_R25D(d) ? 0x0008 : 0); + + /* Software handles checksums and VLAN headers; RSS and VLAN stripping stay off. */ + RGE_CLRBIT_4(d, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); + RGE_CLRBIT_2(d, RGE_CPLUSCMD, 0x0060); + RGE_WRITE_2(d, RGE_RXMAXSIZE, RTL_MAX_FRAME + 4); + RGE_CLRBIT_1(d, RGE_PPSW, 0x08); + RGE_WRITE_4(d, RGE_MAR0, 0xffffffffu); + RGE_WRITE_4(d, RGE_MAR4, 0xffffffffu); + RGE_WRITE_4(d, RGE_RXCFG, rxconf | RGE_RXCFG_INDIV | RGE_RXCFG_MULTI | RGE_RXCFG_BROAD); + rge_disable_aspm_clkreq(d); + RGE_CLRBIT_1(d, RGE_EECMD, RGE_EECMD_WRITECFG); + if (!d->io_error) rtl_delay_us(d, 10); + if (rge_autoneg(d)) return d->io_error; + RGE_WRITE_4(d, RGE_IMR, 0); + RGE_WRITE_4(d, RGE_ISR, RGE_READ_4(d, RGE_ISR)); + __atomic_thread_fence(__ATOMIC_RELEASE); + RGE_WRITE_1(d, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); + return d->io_error; +} +/** @brief Disable and reset RTL8125 DMA before the owner releases its resources. + * @param d Identified mapped device, including partial initialization. + * @return Zero on confirmed quiescence, or negative errno requiring retention. + */ +int rtl8125_stop(struct rtl_device *d) +{ + if (!d->registers) return 0; + int first_error = d->io_error; + d->io_error = 0; /* Stop must still be attempted after an initialization error. */ + int rc = rge_reset(d); + if (!rc) RGE_MAC_CLRBIT(d, 0xc0ac, 0x1f80); + if (!rc) rc = d->io_error; + if (first_error) d->io_error = first_error; + return rc; +} diff --git a/drivers/net/r8169/rtl8125_regs.h b/drivers/net/r8169/rtl8125_regs.h new file mode 100644 index 00000000..13d07f3e --- /dev/null +++ b/drivers/net/r8169/rtl8125_regs.h @@ -0,0 +1,81 @@ +/* $OpenBSD: if_rgereg.h,v 1.21 2026/11/05 07:54:52 kevlo Exp $ */ +/* + * Copyright (c) 2019, 2020, 2025, 2026 + * Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef RELIEFNT_RTL8125_REGS_H +#define RELIEFNT_RTL8125_REGS_H +#define RGE_MAC0 0x0000 +#define RGE_MAC4 0x0004 +#define RGE_MAR0 0x0008 +#define RGE_MAR4 0x000c +#define RGE_TXDESC_ADDR_LO 0x0020 +#define RGE_TXDESC_ADDR_HI 0x0024 +#define RGE_INT_CFG0 0x0034 +#define RGE_CMD 0x0037 +#define RGE_IMR 0x0038 +#define RGE_ISR 0x003c +#define RGE_TXCFG 0x0040 +#define RGE_RXCFG 0x0044 +#define RGE_EECMD 0x0050 +#define RGE_CFG1 0x0052 +#define RGE_CFG2 0x0053 +#define RGE_CFG5 0x0056 +#define RGE_TDFNR 0x0057 +#define RGE_TIMERINT0 0x0058 +#define RGE_TIMERINT1 0x005c +#define RGE_CSIDR 0x0064 +#define RGE_CSIAR 0x0068 +#define RGE_PMCH 0x006f +#define RGE_EPHYAR 0x0080 +#define RGE_TIMERINT2 0x008c +#define RGE_MACOCP 0x00b0 +#define RGE_PHYOCP 0x00b8 +#define RGE_DLLPR 0x00d0 +#define RGE_TWICMD 0x00d2 +#define RGE_MCUCMD 0x00d3 +#define RGE_RXMAXSIZE 0x00da +#define RGE_CPLUSCMD 0x00e0 +#define RGE_IM 0x00e2 +#define RGE_RXDESC_ADDR_LO 0x00e4 +#define RGE_RXDESC_ADDR_HI 0x00e8 +#define RGE_PPSW 0x00f2 +#define RGE_TIMERINT3 0x00f4 +#define RGE_INTMITI(i) (0x0a00 + (i) * 4) +#define RGE_RSS_CTRL 0x4500 +#define RGE_RXQUEUE_CTRL 0x4800 +#define RGE_EEE_TXIDLE_TIMER 0x6048 +#define RGE_CMD_TXENB 0x04 +#define RGE_CMD_RXENB 0x08 +#define RGE_CMD_RESET 0x10 +#define RGE_CMD_STOPREQ 0x80 +#define RGE_RXCFG_INDIV 0x02 +#define RGE_RXCFG_MULTI 0x04 +#define RGE_RXCFG_BROAD 0x08 +#define RGE_RXCFG_VLANSTRIP 0x00c00000 +#define RGE_EECMD_WRITECFG 0xc0 +#define RGE_CFG1_SPEED_DOWN 0x10 +#define RGE_CFG2_CLKREQ_EN 0x80 +#define RGE_CFG5_PME_STS 0x01 +#define RGE_MCUCMD_RXFIFO_EMPTY 0x10 +#define RGE_MCUCMD_TXFIFO_EMPTY 0x20 +#define RGE_MCUCMD_IS_OOB 0x80 +#define RGE_CPLUSCMD_RXCSUM 0x0020 +#define RGE_ADV_2500TFDX 0x0080 +#define RGE_MAC_R25D_1_RCODE_VER 0x0027 +#define RGE_MAC_R25D_2_RCODE_VER 0x0031 +#define RGE_MAC_R25_RCODE_VER 0x0b33 +#define RGE_MAC_R25B_RCODE_VER 0x0b99 +#endif diff --git a/drivers/net/r8169/rtl8168.c b/drivers/net/r8169/rtl8168.c new file mode 100644 index 00000000..84058551 --- /dev/null +++ b/drivers/net/r8169/rtl8168.c @@ -0,0 +1,452 @@ +/* SPDX-License-Identifier: BSD-4-Clause */ +/* + * The RTL8168 initialization and PHY register sequences are adapted from + * OpenBSD re.c, rtl81x9reg.h and rgephy.c, at commit + * 7779d12194498048b288afda664dd6271a2ec016. + * + * Copyright (c) 1997, 1998-2003 + * Bill Paul . All rights reserved. + * Copyright (c) 1997, 1998 + * Bill Paul . All rights reserved. + * Copyright (c) 2003 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "internal.h" +#include + +/* Offsets are for the PCI Express gigabit MAC, not RTL8125. */ +#define R_ID0 0x00u +#define R_ID4 0x04u +#define R_MAR0 0x08u +#define R_MAR4 0x0cu +#define R_TX_DESC_LO 0x20u +#define R_TX_DESC_HI 0x24u +#define R_COMMAND 0x37u +#define R_TX_POLL 0x38u +#define R_IMR 0x3cu +#define R_ISR 0x3eu +#define R_TX_CONFIG 0x40u +#define R_RX_CONFIG 0x44u +#define R_MISSED 0x4cu +#define R_CFG_LOCK 0x50u +#define R_CFG1 0x52u +#define R_CFG3 0x54u +#define R_CFG4 0x55u +#define R_PHYAR 0x60u +#define R_PMCH 0x6fu +#define R_MAX_RX 0xdau +#define R_CPLUS 0xe0u +#define R_RX_DESC_LO 0xe4u +#define R_RX_DESC_HI 0xe8u +#define R_EARLY_TX 0xecu +#define R_MISC 0xf0u + +#define CMD_TX 0x04u +#define CMD_RX 0x08u +#define CMD_RESET 0x10u +#define CMD_STOP 0x80u +#define PHY_BUSY 0x80000000u +#define PHY_RESET 0x8000u +#define TX_QUEUE_EMPTY 0x00000800u +#define TX_NORMAL_POLL 0x40u +#define RX_ACCEPT_MASK 0x0000000fu +#define RX_FILTER 0x0000000eu +#define RX_BASE_CONFIG 0x0000ff00u +#define TX_BASE_CONFIG 0x03000700u +#define CPLUS_BASE 0x0089u +#define HWREV_MASK 0x7c800000u +#define SPIN_BIT 0x00400000u +#define POLL_LIMIT 100u + +#define Q_PHY_PM (1u << 0) +#define Q_CMD_STOP (1u << 1) +#define Q_WAIT_TXQ (1u << 2) +#define Q_WAIT_TXPOLL (1u << 3) +#define Q_EARLY_OFF (1u << 4) +#define Q_EARLY_OFF_V2 (1u << 5) +#define Q_RXDV_GATE (1u << 6) +#define Q_JUMBO_V2 (1u << 7) + +enum rtl8168_revision { + REV_B1 = 1, REV_B2, REV_B3, REV_C, REV_C2, REV_CP, REV_D, + REV_DP, REV_E, REV_E_VL, REV_F, REV_G, REV_GU, REV_H, REV_EP, REV_FP +}; + +/** @brief Save the first initialization or shutdown error. + * @param d Exclusively owned device. @param error Negative errno. + * @return The supplied errno; a prior diagnostic is not overwritten. + */ +static int rtl8168_error(struct rtl_device *d, int error) +{ + if (!d->io_error) + d->io_error = error; + return error; +} + +/** @brief Reset the MAC and wait for the device to acknowledge completion. + * @param d Mapped device in task context with no spinlock held. + * @return Zero or -ETIMEDOUT; a failed reset does not establish DMA quiescence. + */ +static int rtl8168_reset(struct rtl_device *d) +{ + rtl_write8(d, R_COMMAND, CMD_RESET); + for (unsigned i = 0; i < POLL_LIMIT; ++i) { + rtl_delay_us(d, 100); + if (!(rtl_read8(d, R_COMMAND) & CMD_RESET)) + return 0; + } + return rtl8168_error(d, -ETIMEDOUT); +} + +/** @brief Write a Clause 22 PHY register through the MAC's PHYAR mailbox. + * @param d Mapped device in task context. @param reg Register index 0 through 31. + * @param value Register value. @return Zero or -ETIMEDOUT. + */ +static int rtl8168_phy_write(struct rtl_device *d, unsigned reg, uint16_t value) +{ + rtl_write32(d, R_PHYAR, PHY_BUSY | (reg << 16) | value); + for (unsigned i = 0; i < POLL_LIMIT; ++i) { + if (!(rtl_read32(d, R_PHYAR) & PHY_BUSY)) { + rtl_delay_us(d, 20); + return 0; + } + rtl_delay_us(d, 25); + } + return rtl8168_error(d, -ETIMEDOUT); +} + +/** @brief Read a Clause 22 PHY register through the bounded PHYAR mailbox. + * @param d Mapped device in task context. @param reg Register index 0 through 31. + * @param value Caller-owned output. @return Zero or -ETIMEDOUT. + */ +static int rtl8168_phy_read(struct rtl_device *d, unsigned reg, uint16_t *value) +{ + rtl_write32(d, R_PHYAR, reg << 16); + for (unsigned i = 0; i < POLL_LIMIT; ++i) { + uint32_t result = rtl_read32(d, R_PHYAR); + if (result & PHY_BUSY) { + *value = (uint16_t)result; + rtl_delay_us(d, 20); + return 0; + } + rtl_delay_us(d, 25); + } + return rtl8168_error(d, -ETIMEDOUT); +} + +/** @brief Apply the OpenBSD DSP workaround to the earliest RTL8169S PHYs. + * @param d Device with a matching revision-zero or revision-one PHY. + * @return Zero or a mailbox error; page zero restoration is attempted on error. + */ +static int rtl8168_phy_legacy_dsp(struct rtl_device *d) +{ + static const struct { + uint8_t reg; + bool update; + uint16_t clear; + uint16_t value; + } operations[] = { + {21, false, 0, 0x1000}, {24, false, 0, 0x65c7}, + {4, true, 0x0800, 0}, {4, true, 0xf000, 0}, + {3, false, 0, 0x00a1}, {2, false, 0, 0x0008}, + {1, false, 0, 0x1020}, {0, false, 0, 0x1000}, + {4, true, 0, 0x0800}, {4, true, 0x0800, 0}, + {4, true, 0xf000, 0x7000}, {3, false, 0, 0xff41}, + {2, false, 0, 0xde60}, {1, false, 0, 0x0140}, + {0, false, 0, 0x0077}, {4, true, 0xf000, 0xa000}, + {3, false, 0, 0xdf01}, {2, false, 0, 0xdf20}, + {1, false, 0, 0xff95}, {0, false, 0, 0xfa00}, + {4, true, 0xf000, 0xb000}, {3, false, 0, 0xff41}, + {2, false, 0, 0xde20}, {1, false, 0, 0x0140}, + {0, false, 0, 0x00bb}, {4, true, 0xf000, 0xf000}, + {3, false, 0, 0xdf01}, {2, false, 0, 0xdf20}, + {1, false, 0, 0xff95}, {0, false, 0, 0xbf00}, + {4, true, 0, 0x0800}, {4, true, 0x0800, 0} + }; + int rc = rtl8168_phy_write(d, 31, 1); + if (!rc) { + for (unsigned i = 0; i < sizeof(operations) / sizeof(operations[0]); ++i) { + uint16_t value = operations[i].value; + if (operations[i].update) { + rc = rtl8168_phy_read(d, operations[i].reg, &value); + if (rc) + break; + value = (value & (uint16_t)~operations[i].clear) | + operations[i].value; + } + rc = rtl8168_phy_write(d, operations[i].reg, value); + if (rc) + break; + } + } + int restore = rtl8168_phy_write(d, 31, 0); + if (!rc) + rc = restore; + if (!rc) + rtl_delay_us(d, 40); + return rc; +} + +/** @brief Wake and reset the copper PHY, then advertise standard link modes. + * @param d Identified mapped device; task context, no spinlock held. + * @return Zero, -EIO, or -ETIMEDOUT. Link negotiation continues asynchronously. + */ +static int rtl8168_setup_phy(struct rtl_device *d) +{ + uint16_t bmcr = 0, id1, id2; + int rc; + + if (d->quirks & Q_PHY_PM) + rtl_write8(d, R_PMCH, rtl_read8(d, R_PMCH) | 0x80u); + rc = rtl8168_phy_write(d, 0x1f, 0); + if (rc) + return rc; + rc = rtl8168_phy_write(d, 0x0e, 0); + if (rc) + return rc; + rc = rtl8168_phy_write(d, 0x00, PHY_RESET); + if (rc) + return rc; + for (unsigned i = 0; i < POLL_LIMIT; ++i) { + rtl_delay_us(d, 1000); + rc = rtl8168_phy_read(d, 0x00, &bmcr); + if (rc) + return rc; + if (bmcr == 0xffffu) + return rtl8168_error(d, -EIO); + if (!(bmcr & PHY_RESET)) + break; + } + if (bmcr & PHY_RESET) + return rtl8168_error(d, -ETIMEDOUT); + + rc = rtl8168_phy_read(d, 2, &id1); + if (rc) + return rc; + rc = rtl8168_phy_read(d, 3, &id2); + if (rc) + return rc; + if ((!id1 && !id2) || (id1 == 0xffffu && id2 == 0xffffu)) + return rtl8168_error(d, -EIO); + if (((id1 == 0x001cu && (id2 & 0xfff0u) == 0xc910u) || + (id1 == 0x0381u && (id2 & 0xfff0u) == 0x3110u)) && + (id2 & 0x000fu) <= 1u) { + rc = rtl8168_phy_legacy_dsp(d); + if (rc) + return rc; + } + + /* CSMA and 10/100 half/full; advertise both 1000BASE-T duplex modes. */ + rc = rtl8168_phy_write(d, 0x04, 0x01e1u); + if (rc) + return rc; + rc = rtl8168_phy_write(d, 0x09, 0x0300u); + if (rc) + return rc; + return rtl8168_phy_write(d, 0x00, 0x1200u); +} + +/** @brief Identify only PCI 10ec:8168 and a known OpenBSD MAC revision family. + * @param d Mapped PCI function with the original, pre-reset TxConfig snapshot. + * @return Zero with revision, name and quirks, or -ENODEV with no chip name. + */ +int rtl8168_identify(struct rtl_device *d) +{ + enum rtl8168_revision rev; + const char *name; + uint32_t flags = 0; + + d->chip_name = 0; + d->chip_revision = 0; + d->quirks = 0; + if (d->pci.vendor_id != 0x10ecu || d->pci.device_id != 0x8168u) + return -ENODEV; + + switch (d->xid & HWREV_MASK) { + case 0x30000000u: rev = REV_B1; name = "RTL8111B/8168B"; break; + case 0x38000000u: + rev = (d->xid & SPIN_BIT) ? REV_B3 : REV_B2; + name = "RTL8111B/8168B"; break; + case 0x3c000000u: + rev = (d->xid & SPIN_BIT) ? REV_C2 : REV_C; + name = "RTL8111C/8168C"; break; + case 0x3c800000u: rev = REV_CP; name = "RTL8111CP/8168CP"; break; + case 0x28000000u: rev = REV_D; name = "RTL8111D/8168D"; break; + case 0x28800000u: rev = REV_DP; name = "RTL8111DP/8168DP"; break; + case 0x2c000000u: rev = REV_E; name = "RTL8111E/8168E"; break; + case 0x2c800000u: rev = REV_E_VL; name = "RTL8111E-VL/8168E-VL"; break; + case 0x48000000u: rev = REV_F; name = "RTL8111F/8168F"; break; + case 0x4c000000u: rev = REV_G; name = "RTL8111G/8168G"; break; + case 0x50800000u: rev = REV_GU; name = "RTL8111GU/8168GU"; break; + case 0x54000000u: rev = REV_H; name = "RTL8111H/8168H"; break; + case 0x50000000u: rev = REV_EP; name = "RTL8111EP/8168EP"; break; + case 0x54800000u: rev = REV_FP; name = "RTL8111FP/8168FP"; break; + default: return -ENODEV; + } + + switch (rev) { + case REV_B1: case REV_B2: case REV_B3: + break; + case REV_DP: + flags = Q_JUMBO_V2 | Q_WAIT_TXPOLL; + break; + case REV_D: case REV_E: + flags = Q_JUMBO_V2 | Q_CMD_STOP | Q_PHY_PM; + break; + case REV_E_VL: case REV_F: + flags = Q_JUMBO_V2 | Q_CMD_STOP | Q_WAIT_TXQ | Q_EARLY_OFF; + break; + case REV_G: case REV_GU: case REV_H: case REV_EP: case REV_FP: + flags = Q_JUMBO_V2 | Q_CMD_STOP | Q_WAIT_TXQ | + Q_EARLY_OFF_V2 | Q_RXDV_GATE; + break; + default: + flags = Q_JUMBO_V2 | Q_CMD_STOP; + break; + } + d->chip_revision = (unsigned)rev; + d->quirks = flags; + d->chip_name = name; + return 0; +} + +/** @brief Reset and configure the classic gigabit rings, filters and copper PHY. + * @param d Identified device with initialized DMA and bus mastering enabled. + * @return Zero after RX/TX enable, or negative errno with DMA retained for stop. + */ +int rtl8168_start(struct rtl_device *d) +{ + uint32_t mac_lo, mac_hi, rxcfg; + int rc; + + rtl_write16(d, R_IMR, 0); + rtl_write16(d, R_ISR, 0xffffu); + rc = rtl8168_reset(d); + if (rc) + return rc; + + /* C+ mode must be the first configuration after reset. */ + rtl_write16(d, R_CPLUS, CPLUS_BASE); + rtl_write16(d, R_IMR, 0); + rtl_write16(d, R_ISR, 0xffffu); + + mac_lo = (uint32_t)d->mac[0] | ((uint32_t)d->mac[1] << 8) | + ((uint32_t)d->mac[2] << 16) | ((uint32_t)d->mac[3] << 24); + mac_hi = (uint32_t)d->mac[4] | ((uint32_t)d->mac[5] << 8); + rtl_write8(d, R_CFG_LOCK, 0xc0u); + rtl_write32(d, R_ID4, mac_hi); + rtl_write32(d, R_ID0, mac_lo); + if (d->quirks & Q_JUMBO_V2) { + rtl_write8(d, R_CFG3, rtl_read8(d, R_CFG3) | 0x04u); + if (d->chip_revision != REV_DP) { + uint8_t jumbo_bit = d->chip_revision == REV_E ? 0x01u : 0x02u; + rtl_write8(d, R_CFG4, rtl_read8(d, R_CFG4) | jumbo_bit); + } + } + rtl_write8(d, R_CFG_LOCK, 0); + + rc = rtl8168_setup_phy(d); + if (rc) + return rc; + + rtl_write32(d, R_RX_DESC_HI, (uint32_t)(d->rx_physical >> 32)); + rtl_write32(d, R_RX_DESC_LO, (uint32_t)d->rx_physical); + rtl_write32(d, R_TX_DESC_HI, (uint32_t)(d->tx_physical >> 32)); + rtl_write32(d, R_TX_DESC_LO, (uint32_t)d->tx_physical); + if (d->quirks & Q_RXDV_GATE) + rtl_write32(d, R_MISC, rtl_read32(d, R_MISC) & ~0x00080000u); + rtl_write32(d, R_TX_CONFIG, TX_BASE_CONFIG); + rtl_write8(d, R_EARLY_TX, 16); + rxcfg = RX_BASE_CONFIG | RX_FILTER; + if (d->quirks & Q_EARLY_OFF) + rxcfg |= 0x00003800u; + else if (d->quirks & Q_EARLY_OFF_V2) + rxcfg |= 0x00000800u; + rtl_write32(d, R_MAR0, 0xffffffffu); + rtl_write32(d, R_MAR4, 0xffffffffu); + rtl_write32(d, R_RX_CONFIG, rxcfg); + rtl_write32(d, R_MISSED, 0); + rtl_write16(d, R_MAX_RX, (d->quirks & Q_JUMBO_V2) ? 16383u : RTL_BUFFER_SIZE); + rtl_write8(d, R_CFG1, rtl_read8(d, R_CFG1) | 0x20u); + + /* Descriptor contents and both halves of their addresses precede DMA. */ + __atomic_thread_fence(__ATOMIC_RELEASE); + rtl_write8(d, R_COMMAND, CMD_TX | CMD_RX); + return 0; +} + +/** @brief Stop RX admission, drain the revision-specific TX path and reset DMA. + * @param d Identified mapped device, including partially initialized devices. + * @return Zero only after successful drain and reset; otherwise retain DMA memory. + */ +int rtl8168_stop(struct rtl_device *d) +{ + uint8_t command; + int rc = 0; + + rtl_write16(d, R_IMR, 0); + rtl_write16(d, R_ISR, 0xffffu); + rtl_write32(d, R_RX_CONFIG, rtl_read32(d, R_RX_CONFIG) & ~RX_ACCEPT_MASK); + command = rtl_read8(d, R_COMMAND); + if (command & (CMD_TX | CMD_RX)) { + if (d->quirks & Q_WAIT_TXPOLL) { + unsigned i; + for (i = 0; i < POLL_LIMIT; ++i) { + if (!(rtl_read8(d, R_TX_POLL) & TX_NORMAL_POLL)) + break; + rtl_delay_us(d, 20); + } + if (i == POLL_LIMIT) + rc = rtl8168_error(d, -ETIMEDOUT); + rtl_write8(d, R_COMMAND, 0); + } else if (d->quirks & Q_CMD_STOP) { + rtl_write8(d, R_COMMAND, CMD_STOP | CMD_TX | CMD_RX); + if (d->quirks & Q_WAIT_TXQ) { + unsigned i; + for (i = 0; i < POLL_LIMIT; ++i) { + if (rtl_read32(d, R_TX_CONFIG) & TX_QUEUE_EMPTY) + break; + rtl_delay_us(d, 100); + } + if (i == POLL_LIMIT) + rc = rtl8168_error(d, -ETIMEDOUT); + } + } else { + rtl_write8(d, R_COMMAND, 0); + } + rtl_delay_us(d, 1000); + } + if (rtl8168_reset(d) && !rc) + rc = -ETIMEDOUT; + rtl_write16(d, R_IMR, 0); + rtl_write16(d, R_ISR, 0xffffu); + return rc; +} diff --git a/scripts/modules-stage.sh b/scripts/modules-stage.sh index 87d564b3..dac05165 100644 --- a/scripts/modules-stage.sh +++ b/scripts/modules-stage.sh @@ -20,6 +20,13 @@ if [ -z "$extmod" ]; then cp "$out/System.map" "$work/lib/modules/$release/System.map" cp "$out/.config" "$work/lib/modules/$release/config" cp "$out/include/config/module.abi" "$work/lib/modules/$release/module.abi" + # Keep binary attribution within the versioned, checksummed kernel payload. + mkdir -p "$work/lib/modules/$release/LICENSES/realtek" + cp "$src/LICENSE" "$src/NOTICE" "$work/lib/modules/$release/LICENSES/" + cp "$src/LICENSES/realtek/OpenBSD-ISC.txt" \ + "$src/LICENSES/realtek/OpenBSD-BSD-4-Clause.txt" \ + "$src/LICENSES/realtek/Realtek-firmware.txt" \ + "$work/lib/modules/$release/LICENSES/realtek/" # Original modinst omits this file when MODULES=n. The all-builtin bundle # still needs an explicit empty module set; no imported rule is changed. if [ ! -f "$work/lib/modules/$release/modules.order" ]; then diff --git a/tools/test_r8169.py b/tools/test_r8169.py new file mode 100644 index 00000000..5d71b174 --- /dev/null +++ b/tools/test_r8169.py @@ -0,0 +1,29 @@ +#!/usr/bin/env python3 +"""Exercise Realtek driver objects using a PCI/MMIO/DMA boundary model.""" +from pathlib import Path +import os +import subprocess +import tempfile + +ROOT = Path(__file__).resolve().parents[1] +MODEL_SOURCES = ["tools/tests/r8169_test.c", *[ + "drivers/net/r8169/" + name + ".c" + for name in ("main", "hardware", "rings", "rtl8168", "rtl8125", "firmware_8125")]] +IO_SOURCES = ["tools/tests/r8169_io_test.c", "drivers/net/r8169/io.c"] + + +def main(): + temporary = Path(os.environ.get("TMPDIR", str(ROOT / "out/tmp"))) + temporary.mkdir(parents=True, exist_ok=True) + with tempfile.TemporaryDirectory(prefix="reliefnt-r8169-", dir=temporary) as directory: + for name, sources in (("r8169", MODEL_SOURCES), ("r8169-io", IO_SOURCES)): + binary = Path(directory) / name + subprocess.run(["clang", "-std=c11", "-O1", "-g", "-Wall", "-Wextra", "-Werror", + "-fsanitize=address,undefined", "-fno-sanitize-recover=all", + "-fno-pie", "-no-pie", "-Iinclude", "-Iinclude/uapi", + *sources, "-o", str(binary)], cwd=ROOT, check=True) + subprocess.run([str(binary)], check=True, timeout=30) + + +if __name__ == "__main__": + main() diff --git a/tools/tests/host-suites.list b/tools/tests/host-suites.list index b6708d6f..f585cde1 100644 --- a/tools/tests/host-suites.list +++ b/tools/tests/host-suites.list @@ -11,6 +11,7 @@ cpu_accounting tools/test_cpu_accounting.py drm tools/test_drm.py e1000 tools/test_e1000.py e1000e tools/test_e1000e.py +r8169 tools/test_r8169.py efi_fs_early tools/test_efi_fs_early.py efi_handoff tools/test_efi_handoff.py efi_acpi_bootstrap tools/test_efi_acpi_bootstrap.py diff --git a/tools/tests/r8169_io_test.c b/tools/tests/r8169_io_test.c new file mode 100644 index 00000000..6e482684 --- /dev/null +++ b/tools/tests/r8169_io_test.c @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Exercise the production register and delay functions at their hardware boundary. */ +#include +#include +#include +#include +#include "../../drivers/net/r8169/internal.h" + +#define TEST_IF (1ULL << 9) +#define TICK_NS 10000000ULL + +enum clock_mode { CLOCK_RUNNING, CLOCK_STALLED, CLOCK_BACKWARD }; + +static enum clock_mode mode; +static uint64_t wall_ns; +static unsigned clock_reads, sleeps; +static bool irq_enabled; +static uint16_t word_port, word_value; +static uint16_t byte_port, dword_port; +static uint8_t byte_value; +static uint32_t dword_value; + +/** @brief Save simulated local IF while confirming that no real lock is taken. */ +void kernel_spin_lock_irqsave(struct kernel_spinlock *lock, uint64_t *flags) +{ + assert(!lock && flags); + *flags = irq_enabled ? TEST_IF : 0; + irq_enabled = false; +} + +/** @brief Restore the IF saved by the real driver's IRQ guard. */ +void kernel_spin_unlock_irqrestore(struct kernel_spinlock *lock, uint64_t flags) +{ + assert(!lock); + irq_enabled = (flags & TEST_IF) != 0; +} + +/** @brief Sample a quantized clock with selectable progress and fault behavior. */ +uint64_t time_uptime_us(void) +{ + assert(!irq_enabled); + ++clock_reads; + assert(clock_reads < 100000); + wall_ns += 250; + if (mode == CLOCK_STALLED) + return 1000; + if (mode == CLOCK_BACKWARD) + return clock_reads == 2 ? 1001 : 1000; + return wall_ns / 1000; +} + +/** @brief Model the production 100 Hz sleep and its IF-cleared return state. */ +static void sleep_ms(uint64_t milliseconds) +{ + uint64_t delta = (milliseconds * 100 + 999) / 1000; + assert(delta != 0); + ++sleeps; + wall_ns = (wall_ns / TICK_NS + delta) * TICK_NS; + irq_enabled = false; +} + +/** @brief Read a modeled legacy byte port. */ +static uint8_t inb(uint16_t port) +{ + byte_port = port; + return byte_value; +} + +/** @brief Write a modeled legacy byte port. */ +static void outb(uint16_t port, uint8_t value) +{ + byte_port = port; + byte_value = value; +} + +/** @brief Read a modeled legacy dword port. */ +static uint32_t inl(uint16_t port) +{ + dword_port = port; + return dword_value; +} + +/** @brief Write a modeled legacy dword port. */ +static void outl(uint16_t port, uint32_t value) +{ + dword_port = port; + dword_value = value; +} + +/** @brief Read a modeled legacy word port. */ +uint16_t x86_64_inw(uint16_t port) +{ + word_port = port; + return word_value; +} + +/** @brief Write a modeled legacy word port. */ +void x86_64_outw(uint16_t value, uint16_t port) +{ + word_port = port; + word_value = value; +} + +static const struct reliefos_driver_kernel_api api = { + .inb = inb, .outb = outb, .inl = inl, .outl = outl, .sleep_ms = sleep_ms, +}; +static struct rtl_device device = { .api = &api }; + +/** @brief Reset the simulated clocks and caller IRQ state for one scenario. */ +static void reset_clock(enum clock_mode next_mode, uint64_t start_ns, bool entry_if) +{ + mode = next_mode; + wall_ns = start_ns; + clock_reads = sleeps = 0; + irq_enabled = entry_if; +} + +/** @brief Require submillisecond delays to progress without a tick-level sleep. */ +static void test_short_delays(void) +{ + static const unsigned waits[] = { 1, 10, 20, 40, 100, 200, 999 }; + static const uint64_t starts[] = { 50000, 50250, 50700, 50999 }; + for (unsigned state = 0; state < 2; ++state) { + for (unsigned i = 0; i < sizeof(waits) / sizeof(waits[0]); ++i) { + for (unsigned j = 0; j < sizeof(starts) / sizeof(starts[0]); ++j) { + reset_clock(CLOCK_RUNNING, starts[j], state != 0); + uint64_t start = wall_ns; + rtl_delay_us(&device, waits[i]); + assert(sleeps == 0); + assert(wall_ns - start >= (uint64_t)waits[i] * 1000); + assert(irq_enabled == (state != 0)); + } + } + reset_clock(CLOCK_RUNNING, 50999, state != 0); + rtl_delay_us(&device, 0); + assert(clock_reads == 0 && sleeps == 0 && irq_enabled == (state != 0)); + } +} + +/** @brief Test partial-first-tick sleep phases including the maximum argument. */ +static void test_tick_sleep_minimum_and_irq_state(void) +{ + static const unsigned waits[] = { 1000, 3000, 9999, 10000, 10001, UINT_MAX }; + static const uint64_t phases[] = { 1, 5000000, 9999999 }; + for (unsigned state = 0; state < 2; ++state) { + for (unsigned i = 0; i < sizeof(waits) / sizeof(waits[0]); ++i) { + for (unsigned j = 0; j < sizeof(phases) / sizeof(phases[0]); ++j) { + reset_clock(CLOCK_RUNNING, TICK_NS * 2 + phases[j], state != 0); + uint64_t start = wall_ns; + rtl_delay_us(&device, waits[i]); + assert(sleeps == 1); + assert(wall_ns - start >= (uint64_t)waits[i] * 1000); + assert(wall_ns - start <= (uint64_t)waits[i] * 1000 + 30000000ULL); + assert(irq_enabled == (state != 0)); + } + } + } +} + +/** @brief The sleep callback's cleared IF must not leak to its caller. */ +static void test_sleep_restores_if(void) +{ + reset_clock(CLOCK_RUNNING, TICK_NS + 1, true); + rtl_delay_us(&device, 1000); + assert(sleeps == 1 && irq_enabled); +} + +/** @brief Clock stalls or reversal must terminate polling and use a full fallback wait. */ +static void test_clock_faults(void) +{ + for (unsigned state = 0; state < 2; ++state) { + for (enum clock_mode fault = CLOCK_STALLED; fault <= CLOCK_BACKWARD; ++fault) { + reset_clock(fault, 3 * TICK_NS - 1, state != 0); + uint64_t start = wall_ns; + rtl_delay_us(&device, 20); + assert(clock_reads > 0 && clock_reads < 100000); + if (fault == CLOCK_BACKWARD) + assert(clock_reads <= 16); + assert(sleeps == 1); + assert(wall_ns - start >= 20000); + assert(irq_enabled == (state != 0)); + } + } +} + +/** @brief Check that MMIO and port reads/writes use the requested width and offset. */ +static void test_register_accesses(void) +{ + uint32_t registers[8] = {0}; + device.io_base = 0; + device.registers = (volatile uint8_t *)registers; + rtl_write8(&device, 1, 0xab); + rtl_write16(&device, 2, 0xcdef); + rtl_write32(&device, 4, 0x12345678); + assert(rtl_read8(&device, 1) == 0xab); + assert(rtl_read16(&device, 2) == 0xcdef); + assert(rtl_read32(&device, 4) == 0x12345678); + + device.io_base = 0xe000; + rtl_write8(&device, 1, 0x56); + rtl_write16(&device, 2, 0x789a); + rtl_write32(&device, 4, 0xbcdef012); + assert(byte_port == 0xe001 && word_port == 0xe002 && dword_port == 0xe004); + assert(rtl_read8(&device, 1) == 0x56 && byte_port == 0xe001); + assert(rtl_read16(&device, 2) == 0x789a && word_port == 0xe002); + assert(rtl_read32(&device, 4) == 0xbcdef012 && dword_port == 0xe004); +} + +/** @brief Run all scenarios, or one named scenario to diagnose a regression. + * @param argc Argument count. @param argv Optional test name. + * @return Zero after the selected assertions pass. + */ +int main(int argc, char **argv) +{ + assert(argc <= 2); + if (argc == 1 || !strcmp(argv[1], "short")) test_short_delays(); + if (argc == 1 || !strcmp(argv[1], "long")) test_tick_sleep_minimum_and_irq_state(); + if (argc == 1 || !strcmp(argv[1], "irq")) test_sleep_restores_if(); + if (argc == 1 || !strcmp(argv[1], "faults")) test_clock_faults(); + if (argc == 1 || !strcmp(argv[1], "registers")) test_register_accesses(); + puts("r8169 I/O and timing tests passed"); + return 0; +} diff --git a/tools/tests/r8169_test.c b/tools/tests/r8169_test.c new file mode 100644 index 00000000..b0f9960f --- /dev/null +++ b/tools/tests/r8169_test.c @@ -0,0 +1,546 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Separate production objects, with only the PCI/MMIO/DMA boundary replaced. */ +#include +#include +#include +#include +#include +#include "../../drivers/net/r8169/internal.h" + +extern const struct reliefos_driver_module r8169_driver_module; + +static uint8_t registers[0x10000]; +static uint16_t mac_ocp[32768], phy_ocp[32768], ephy[128], phy[32]; +static uint32_t csi[1024]; +static uint16_t device_id, pci_command, original_command; +static uint16_t pmcsr; +static bool power_capability; +static unsigned live, maps, unmaps, allocation_attempts, allocation_failure; +static unsigned kicks, resets, mdio_accesses; +static int reset_stuck, indirect_stuck, mapping_failure, registration_error, teardown_error; +static uint64_t next_physical = 0x140000000ULL; +static const uint64_t bar = 0xc000000000ULL; +static const struct reliefos_driver_e1000_ops *network; +static struct allocation { uint64_t physical; unsigned pages; void *bytes; } memory[8]; + +static uint32_t raw32(unsigned offset) +{ + uint32_t value; + assert(offset + 4 <= sizeof(registers)); + memcpy(&value, registers + offset, 4); + return value; +} + +static void store32(unsigned offset, uint32_t value) +{ + assert(offset + 4 <= sizeof(registers)); + memcpy(registers + offset, &value, 4); +} + +void kernel_spin_lock_irqsave(struct kernel_spinlock *lock, uint64_t *flags) +{ + assert(!lock->state); + lock->state = 1; + *flags = 0; +} + +void kernel_spin_unlock_irqrestore(struct kernel_spinlock *lock, uint64_t flags) +{ + (void)flags; + assert(lock->state); + lock->state = 0; +} + +uint8_t rtl_read8(const struct rtl_device *d, unsigned offset) +{ + assert((d->registers == registers || d->io_base == 0xe000) && offset < d->mmio_bytes); + if (offset == 0x37 && !reset_stuck) + registers[offset] = (registers[offset] & ~0x90u) | 1; + return registers[offset]; +} + +uint16_t rtl_read16(const struct rtl_device *d, unsigned offset) +{ + assert((d->registers == registers || d->io_base == 0xe000) && + !(offset & 1) && offset + 2 <= d->mmio_bytes); + uint16_t value; + memcpy(&value, registers + offset, 2); + return value; +} + +uint32_t rtl_read32(const struct rtl_device *d, unsigned offset) +{ + assert((d->registers == registers || d->io_base == 0xe000) && + !(offset & 3) && offset + 4 <= d->mmio_bytes); + if (offset == 0x40) + return raw32(offset) | 0x800; /* No outstanding TX DMA in the boundary model. */ + return raw32(offset); +} + +void rtl_write8(struct rtl_device *d, unsigned offset, uint8_t value) +{ + assert((d->registers == registers || d->io_base == 0xe000) && offset < d->mmio_bytes); + if (offset == 0x37 && (value & 0x10)) + ++resets; + if (offset == 0x38 && device_id == 0x8168) { + assert(value == 0x40); + ++kicks; + return; + } + registers[offset] = value; +} + +void rtl_write16(struct rtl_device *d, unsigned offset, uint16_t value) +{ + assert((d->registers == registers || d->io_base == 0xe000) && + !(offset & 1) && offset + 2 <= d->mmio_bytes); + if (offset == 0x90 && device_id == 0x8125) + ++kicks; + memcpy(registers + offset, &value, 2); +} + +void rtl_write32(struct rtl_device *d, unsigned offset, uint32_t value) +{ + assert((d->registers == registers || d->io_base == 0xe000) && + !(offset & 3) && offset + 4 <= d->mmio_bytes); + unsigned reg = (value >> 16) & 0x7fff; + uint16_t data = value; + store32(offset, value); + if (offset == 0xb0) { + if (value & 0x80000000u) + mac_ocp[reg] = data; + else + store32(offset, mac_ocp[reg]); + } else if (offset == 0xb8) { + ++mdio_accesses; + if (indirect_stuck) + return; + if (value & 0x80000000u) { + phy_ocp[reg] = data; + if (reg == 0xa400 / 2) + phy_ocp[reg] &= ~0x8000u; + if (reg == 0xb820 / 2) { + if (data & 0x10) + phy_ocp[0xb800 / 2] |= 0x40; + else + phy_ocp[0xb800 / 2] &= ~0x40u; + } + store32(offset, value & ~0x80000000u); + } else { + store32(offset, 0x80000000u | phy_ocp[reg]); + } + } else if (offset == 0x60) { + ++mdio_accesses; + if (indirect_stuck) + return; + reg &= 31; + if (value & 0x80000000u) { + phy[reg] = data; + if (reg == 0) + phy[reg] &= ~0x8000u; + store32(offset, value & ~0x80000000u); + } else { + store32(offset, 0x80000000u | phy[reg]); + } + } else if (offset == 0x80) { + if (indirect_stuck) + return; + reg &= 127; + if (value & 0x80000000u) { + ephy[reg] = data; + store32(offset, value & ~0x80000000u); + } else { + store32(offset, 0x80000000u | ephy[reg]); + } + } else if (offset == 0x68) { + if (indirect_stuck) + return; + reg = (value & 0xfff) / 4; + if (value & 0x80000000u) { + csi[reg] = raw32(0x64); + store32(offset, value & ~0x80000000u); + } else { + store32(0x64, csi[reg]); + store32(offset, value | 0x80000000u); + } + } +} + +void rtl_delay_us(struct rtl_device *d, unsigned us) +{ + (void)d; + (void)us; +} + +static uint64_t allocate(uint32_t pages, uint64_t mask) +{ + ++allocation_attempts; + if (allocation_attempts == allocation_failure) + return 0; + for (unsigned i = 0; i < 8; ++i) { + if (memory[i].physical) + continue; + void *bytes = calloc(pages, 4096); + assert(bytes); + uint64_t physical = next_physical; + next_physical += (uint64_t)pages * 4096; + assert(physical + (uint64_t)pages * 4096 - 1 <= mask); + memory[i] = (struct allocation){physical, pages, bytes}; + ++live; + return physical; + } + abort(); +} + +static void release(uint64_t physical, uint32_t pages) +{ + assert(!(pci_command & 4)); + for (unsigned i = 0; i < 8; ++i) { + if (memory[i].physical != physical) + continue; + assert(memory[i].pages == pages); + free(memory[i].bytes); + memory[i] = (struct allocation){0}; + --live; + return; + } + abort(); +} + +static void *alias(uint64_t physical) +{ + for (unsigned i = 0; i < 8; ++i) + if (memory[i].physical && physical >= memory[i].physical && + physical - memory[i].physical < (uint64_t)memory[i].pages * 4096) + return (uint8_t *)memory[i].bytes + physical - memory[i].physical; + return NULL; +} + +static int find(uint16_t vendor, uint16_t id, struct reliefos_driver_pci_device *out) +{ + if (vendor != 0x10ec || id != device_id) + return -19; + *out = (struct reliefos_driver_pci_device){.vendor_id = vendor, .device_id = id, + .bus = 2, .slot = 3, .class_code = 2}; + return 0; +} + +static uint16_t pci_read16(uint8_t b, uint8_t s, uint8_t f, uint8_t offset) +{ + assert(b == 2 && s == 3 && f == 0); + if (power_capability) { + if (offset == 6) + return 0x10; + if (offset == 0x40) + return 1; + if (offset == 0x44) + return pmcsr; + } + return offset == 4 ? pci_command : 0; +} + +static void pci_write16(uint8_t b, uint8_t s, uint8_t f, uint8_t offset, uint16_t value) +{ + assert(b == 2 && s == 3 && f == 0); + if (power_capability && offset == 0x44) { + pmcsr = (value & ~0x8000u) | (pmcsr & ~value & 0x8000u); + return; + } + assert(offset == 4); + pci_command = value; +} + +static uint32_t pci_read32(uint8_t b, uint8_t s, uint8_t f, uint8_t offset) +{ + assert(b == 2 && s == 3 && f == 0); + if (power_capability && offset == 0x34) + return 0x40; + if (offset == 0x10) + return 0xe001; + if (offset == 0x18) + return (uint32_t)bar | 4; + if (offset == 0x1c) + return bar >> 32; + return 0; +} + +static void *map(uint64_t physical, uint64_t bytes) +{ + assert(physical == bar && bytes <= sizeof(registers) && !(pci_command & 7)); + if (mapping_failure) + return NULL; + ++maps; + return registers; +} + +static void unmap(void *pointer, uint64_t bytes) +{ + assert(pointer == registers && bytes <= sizeof(registers)); + assert(!(pci_command & 4) && !live && maps == unmaps + 1); + ++unmaps; +} + +static void sleep_ms(uint64_t milliseconds) +{ + (void)milliseconds; +} + +static uint8_t io_inb(uint16_t port) +{ + assert(port >= 0xe000 && port < 0xe100); + return registers[port - 0xe000]; +} + +static void io_outb(uint16_t port, uint8_t value) +{ + assert(port >= 0xe000 && port < 0xe100); + registers[port - 0xe000] = value; +} + +static uint32_t io_inl(uint16_t port) +{ + assert(port >= 0xe000 && port <= 0xe0fc); + return raw32(port - 0xe000); +} + +static void io_outl(uint16_t port, uint32_t value) +{ + assert(port >= 0xe000 && port <= 0xe0fc); + store32(port - 0xe000, value); +} + +static int register_network(const struct reliefos_driver_e1000_ops *ops) +{ + if (registration_error) + return registration_error; + assert(!network); + network = ops; + return 0; +} + +static void log_message(enum console_log_level level, const char *format, ...) +{ + (void)level; + va_list args; + va_start(args, format); + vprintf(format, args); + va_end(args); +} + +static void failed_stop(int error) +{ + teardown_error = error; +} + +static const struct reliefos_driver_kernel_api api = { + .abi_version = RELIEFOS_DRIVER_ABI_VERSION, .struct_size = sizeof(api), + .pci_find = find, .pci_read16 = pci_read16, .pci_write16 = pci_write16, + .pci_read32 = pci_read32, .map_mmio = map, .unmap_mmio = unmap, + .alloc_dma = allocate, .free_dma = release, .phys_to_virt = alias, + .sleep_ms = sleep_ms, .console_log = log_message, + .register_e1000 = register_network, .report_teardown_failure = failed_stop, +}; + +static void fixture(uint16_t id, uint32_t xid) +{ + assert(!live && maps == unmaps); + memset(registers, 0, sizeof(registers)); + memset(mac_ocp, 0, sizeof(mac_ocp)); + memset(phy_ocp, 0, sizeof(phy_ocp)); + memset(phy, 0, sizeof(phy)); + memset(ephy, 0, sizeof(ephy)); + memset(csi, 0, sizeof(csi)); + device_id = id; + pci_command = original_command = 7; + power_capability = false; + pmcsr = 0; + allocation_attempts = allocation_failure = kicks = resets = mdio_accesses = 0; + reset_stuck = indirect_stuck = mapping_failure = registration_error = teardown_error = 0; + network = NULL; + store32(0x40, xid); + store32(0, 0x33221102); + store32(4, 0x5544); + store32(0x19e0, 0x33221102); + store32(0x19e4, 0x5544); + registers[0x6c] = 2; + registers[0xd3] = 0x32; + registers[0xe2] = 3; + registers[0xe3] = 1; + phy[2] = 0x001c; + phy[3] = 0xc916; + mac_ocp[0xe00e / 2] = 0x2000; + phy_ocp[0xa420 / 2] = 3; +} + +static void finish(void) +{ + network = NULL; + r8169_driver_module.fini(); + uint16_t expected = device_id ? original_command & ~4u : original_command; + assert(!teardown_error && !live && maps == unmaps && pci_command == expected); +} + +static void ring_tests(enum rtl_family family) +{ + fixture(family == RTL_FAMILY_8125 ? 0x8125 : 0x8168, 0); + struct rtl_device d = {.api = &api, .registers = registers, + .family = family, .active = true, .mmio_bytes = sizeof(registers)}; + assert(!rtl_allocate_rings(&d) && live == 4); + assert(d.rx_physical > UINT32_MAX && d.rx[0].address > UINT32_MAX); + assert(d.rx[RTL_RX_COUNT - 1].command & RTL_DESC_EOR); + uint8_t input[RTL_MAX_FRAME], output[RTL_MAX_FRAME + 1]; + memset(input, 0xa5, sizeof(input)); + uint32_t length = 99; + assert(rtl_receive(&d, output, sizeof(output), &length) == 0 && !length); + assert(rtl_send(&d, NULL, 60) == -22); + assert(rtl_send(&d, input, 13) == -22); + assert(rtl_send(&d, input, RTL_MAX_FRAME + 1) == -90); + registers[0x6c] = 0; + assert(rtl_send(&d, input, 60) == -100); + registers[0x6c] = 2; + for (unsigned cycle = 0; cycle < 4; ++cycle) { + for (unsigned i = 0; i < RTL_TX_COUNT - 1; ++i) + assert(rtl_send(&d, input, i == 0 ? 14 : sizeof(input)) == 0); + assert(rtl_send(&d, input, 60) == -11); + for (unsigned i = 0; i < RTL_TX_COUNT; ++i) { + uint32_t command = d.tx[i].command; + if (!(command & RTL_DESC_OWN)) + continue; + assert((command & (RTL_DESC_FIRST | RTL_DESC_LAST)) == + (RTL_DESC_FIRST | RTL_DESC_LAST)); + unsigned bytes = command & 0x3fff; + assert(bytes == 60 || bytes == sizeof(input)); + if (bytes == 60) + for (unsigned j = 14; j < bytes; ++j) + assert(d.tx_data[i * RTL_BUFFER_SIZE + j] == 0); + assert((command & RTL_DESC_EOR) == (i == RTL_TX_COUNT - 1 ? RTL_DESC_EOR : 0)); + d.tx[i].command &= ~RTL_DESC_OWN; + } + } + assert(kicks == 4 * (RTL_TX_COUNT - 1)); + for (unsigned i = 0; i < RTL_RX_COUNT * 2; ++i) { + unsigned index = d.rx_next; + memcpy(d.rx_data + index * RTL_BUFFER_SIZE, input, sizeof(input)); + memset(output, 0, sizeof(output)); + /* Reserved classic status bits are not an RX error indication. */ + d.rx[index].command = RTL_DESC_FIRST | RTL_DESC_LAST | (1u << 23) | + (1u << 24) | (sizeof(input) + 4); + assert(rtl_receive(&d, output, sizeof(output), &length) == 1); + assert(length == sizeof(input) && !memcmp(input, output, length)); + assert(d.rx[index].command & RTL_DESC_OWN); + assert((d.rx[index].command & RTL_DESC_EOR) == + (index == RTL_RX_COUNT - 1 ? RTL_DESC_EOR : 0)); + } + const uint32_t bad[] = { + RTL_DESC_FIRST | RTL_DESC_LAST | RTL_RX_ERROR | 64, + RTL_DESC_FIRST | RTL_DESC_LAST | (1u << 19) | 64, + RTL_DESC_FIRST | RTL_DESC_LAST | 3, + RTL_DESC_FIRST | RTL_DESC_LAST | (RTL_BUFFER_SIZE + 1), + RTL_DESC_FIRST | 64, RTL_DESC_LAST | 64, + }; + for (unsigned i = 0; i < sizeof(bad) / sizeof(bad[0]); ++i) { + unsigned index = d.rx_next; + d.rx[index].command = bad[i]; + assert(rtl_receive(&d, output, sizeof(output), &length) < 0 && !length); + assert(d.rx[index].command & RTL_DESC_OWN); + } + d.rx[d.rx_next].command = RTL_DESC_FIRST | RTL_DESC_LAST | 100; + assert(rtl_receive(&d, output, 10, &length) == -90 && !length); + pci_command &= ~4u; + rtl_free_rings(&d); + assert(!live); +} + +static void lifecycle(uint16_t id, uint32_t xid) +{ + fixture(id, xid); + int rc = r8169_driver_module.init(&api); + if (rc) + fprintf(stderr, "init id=%04x xid=%08x failed %d\n", id, xid, rc); + assert(rc == 0 && network && live == 4 && mdio_accesses); + assert(network->is_ready()); + struct reliefos_driver_e1000_info info; + network->get_info(&info); + assert(info.present && info.active && info.vendor_id == 0x10ec && info.device_id == id); + assert(!memcmp(info.mac, "\x02\x11\x22\x33\x44\x55", 6)); + assert(raw32(0x20) && raw32(0x24) && raw32(0xe4) && raw32(0xe8)); + assert((raw32(0x44) & 0xf) == 0xe); + assert(!(registers[0xe0] & 0x60)); + if (id == 0x8125) { + assert(!(raw32(0x44) & (1u << 24)) && !(mac_ocp[0xeb58 / 2] & 1)); + assert(phy_ocp[0xa5d4 / 2] & 0x80); + assert(phy_ocp[0xa408 / 2] == 0x0de1 && phy_ocp[0xa412 / 2] == 0x0300); + } + registers[0x6c] = 0; + assert(!network->is_ready()); + registers[0x6c] = 2; + assert(network->is_ready()); + reset_stuck = 1; + network = NULL; + r8169_driver_module.fini(); + assert(teardown_error < 0 && live == 4 && maps == unmaps + 1); + reset_stuck = teardown_error = 0; + finish(); + fixture(id, xid); + registration_error = -16; + assert(r8169_driver_module.init(&api) == -16 && !network); + finish(); + for (unsigned failure = 1; failure <= 4; ++failure) { + fixture(id, xid); + allocation_failure = failure; + assert(r8169_driver_module.init(&api) == -12 && !network); + finish(); + } + fixture(id, xid); + indirect_stuck = 1; + assert(r8169_driver_module.init(&api) < 0 && !network); + indirect_stuck = 0; + finish(); +} + +int main(void) +{ + assert(r8169_driver_module.kind == RELIEFOS_DRIVER_KIND_NETWORK); + ring_tests(RTL_FAMILY_8168); + ring_tests(RTL_FAMILY_8125); + fixture(0, 0); + assert(r8169_driver_module.init(&api) == -19); + finish(); + fixture(0x8168, 0); + assert(r8169_driver_module.init(&api) == -19); + finish(); + fixture(0x8125, 0); + assert(r8169_driver_module.init(&api) == -19); + finish(); + fixture(0x8168, 0x54100000); + mapping_failure = 1; + assert(r8169_driver_module.init(&api) == -12); + finish(); + const uint32_t gigabit[] = { + 0x30000000, 0x38000000, 0x38400000, 0x3c000000, 0x3c400000, + 0x3c800000, 0x28000000, 0x28800000, 0x2c000000, 0x2c800000, + 0x48000000, 0x4c000000, 0x50800000, 0x54100000, 0x50000000, 0x54800000 + }; + for (unsigned i = 0; i < sizeof(gigabit) / sizeof(gigabit[0]); ++i) + lifecycle(0x8168, gigabit[i]); + lifecycle(0x8125, 0x64100000); + lifecycle(0x8125, 0x60900000); + lifecycle(0x8125, 0x68800000); + lifecycle(0x8125, 0x68900000); + /* A sub-page memory BAR can use the same device's legacy I/O BAR. */ + fixture(0x8168, 0x30000000); + mapping_failure = 1; + power_capability = true; + pmcsr = 0x8003; /* D3hot and a pending PME status, which must survive. */ + struct reliefos_driver_kernel_api port_api = api; + port_api.inb = io_inb; + port_api.outb = io_outb; + port_api.inl = io_inl; + port_api.outl = io_outl; + assert(r8169_driver_module.init(&port_api) == 0 && network && maps == unmaps && live == 4); + assert((pci_command & 7) == 5); + assert(pmcsr == 0x8000); + finish(); + puts("r8169: DMA ring wrap, framing, high addresses, failure rollback and lifecycle passed"); + return 0; +}