From 0479f8b8290294218779ae8db10c321e59943c4a Mon Sep 17 00:00:00 2001
From: XYenChi <oriachiuan@gmail.com>
Date: Sun, 19 Apr 2026 23:32:28 +0800
Subject: [PATCH 01/21] Add RISC-V Blocklist (#1)

* Add RISC-V 64 BLOCK_LIST

* Skip long time testcase

Co-authored-by: Cursor <cursoragent@cursor.com>
---
 test/run_test.py    | 47 +++++++++++++++++++++++++++++++++++++++++++++
 test/test_linalg.py |  1 +
 2 files changed, 48 insertions(+)

diff --git a/test/run_test.py b/test/run_test.py
index be7973e119c65..45e64cd912960 100755
--- a/test/run_test.py
+++ b/test/run_test.py
@@ -120,6 +120,7 @@ def upload_adhoc_failure_json(*args, **kwargs):
 INDUCTOR_TEST_PREFIX = "inductor"
 IS_SLOW = "slow" in TEST_CONFIG or "slow" in BUILD_ENVIRONMENT
 IS_S390X = platform.machine() == "s390x"
+IS_RISCV64 = platform.machine() == "riscv64"
 
 
 # Note [ROCm parallel CI testing]
@@ -295,6 +296,45 @@ def __contains__(self, item):
     "test_xpu",
 ]
 
+RISCV64_BLOCKLIST = [
+    # disable distributed related test
+    "inductor/test_distributed_patterns"
+    "fx/test_dce_pass"
+    "export/test_cpp_serdes"
+    "export/test_export"
+    "export/test_export_strict"
+    "export/test_export_training_ir_to_run_decomp"
+    "export/test_retraceability"
+    "export/test_serdes"
+    "export/test_strict_export_v2"
+    "test_public_bindings"
+    # quantized engine NoQEngine is not supported
+    "test_torch"
+    "ao/sparsity/test_composability"
+    # QNNPACK is not supported
+    "export/test_converter"
+    # record_contex_cpp is not support on non-linux non-x86_64 platforms
+    "torch_np/numpy_tests/core/test_numeric"
+    # Failed to import torch.distributed.run: cannot import name 'Store' from 'torch.distributed'
+    "test_testing"
+    # TODO:L1 cache size = 0, need to fix
+    "inductor/test_cpu_select_algorithm"
+    "inductor/test_aot_inductor_arrayref"
+    "inductor/test_cpu_repro"
+    # TODO:scalar value not equal, need to fix
+    "profiler/test_profiler"
+    # TODO precision
+    "test_binary_ufuncs"
+    "test_decomp"
+    # TODO no CUDA related module
+    "quantization/core/test_workflow_module"  # TestFakeQuantize.test_fq_module_per_channel
+    "quantization/core/test_workflow_ops"
+    "quantization/core/test_quantized_op"
+    # z3-solver build fail
+    "test_proxy_tensor"
+]
+
+
 # The tests inside these files should never be run in parallel with each other
 RUN_PARALLEL_BLOCKLIST = [
     "test_extension_utils",
@@ -1980,6 +2020,13 @@ def get_selected_tests(options) -> list[str]:
             selected_tests,
             "Skip distributed tests on s390x",
         )
+    elif IS_RISCV64:
+        selected_tests = exclude_tests(RISCV64_BLOCKLIST, selected_tests, "on riscv64")
+        selected_tests = exclude_tests(
+            DISTRIBUTED_TESTS,
+            selected_tests,
+            "Skip distributed tests on riscv64",
+        )
 
     # skip all distributed tests if distributed package is not available.
     if not dist.is_available():
diff --git a/test/test_linalg.py b/test/test_linalg.py
index 7f5d873c03d64..4bdd3dd2d1543 100644
--- a/test/test_linalg.py
+++ b/test/test_linalg.py
@@ -7996,6 +7996,7 @@ def test_matrix_exp_backward_input_validation(self, device, dtype):
         with self.assertRaisesRegex(RuntimeError, "must be batches of square matrices"):
             torch.ops.aten.matrix_exp_backward(non_square, grad_non_square)
 
+    @slowTest
     @skipCUDAIfNoMagmaAndNoLinalgsolver
     @skipCPUIfNoLapack
     @dtypes(torch.float, torch.double, torch.complex64, torch.complex128)

From fb0bd0a687c1660d9b11a860115582e4b73b55fc Mon Sep 17 00:00:00 2001
From: Bo YU <tsu.yubo@gmail.com>
Date: Wed, 22 Apr 2026 08:10:52 +0000
Subject: [PATCH 02/21] add riscv64 ci

---
 .github/workflows/ci-riscv64.yml | 99 ++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 .github/workflows/ci-riscv64.yml

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
new file mode 100644
index 0000000000000..ffc859265b3c9
--- /dev/null
+++ b/.github/workflows/ci-riscv64.yml
@@ -0,0 +1,99 @@
+# Note: this runner is provided externally, so we minimize its access to
+# secrets.
+on:
+  push:
+    branches: [riscv]
+
+  pull_request_target:
+    types: [opened, synchronize, reopened]
+  
+
+name: CI (riscv64)
+
+permissions:
+  contents: read
+  # No permissions to secrets.
+
+concurrency:
+  group: ${{ github.workflow }}-${{ github.head_ref || github.run_id }}
+  cancel-in-progress: true
+
+# FIXME: Drop this
+env:
+  RUSTFLAGS: -D warnings
+  CARGO_TERM_COLOR: always
+
+jobs:
+  build:
+    name: Build and test
+    runs-on: [self-hosted, linux, amd64]
+    # This is in its own separate environment.
+    environment: riscv64
+    steps:
+      - name: Checkout repo
+        uses: actions/checkout@v4
+        with:
+          fetch-depth: 0   # merge-base
+
+      - name: Extract PR info
+        run: |
+          echo "BASE_SHA=${{ github.event.pull_request.base.sha }}" >> $GITHUB_ENV
+          echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> GITHUB_ENV
+          echo "PR_NUMBER=${{ github.event.pull_request.number }}" >> GITHUB_ENV
+
+      - name: Diff base and head
+        run: |
+          if [ "${{ github.event_name }}" = "pull_request" ]; then
+          echo "Push PR build"
+            BASE_REF="${{ github.base_ref }}"
+            HEAD_REF="${{ github.head_ref }}"
+
+            echo "Base ref: $BASE_REF"
+            echo "Head ref: $HEAD_REF"
+
+            # 强约束: PR 必须基于 riscv
+            if [ "$BASE_REF" != "riscv" ]; then
+              echo "ERROR: PR must target 'riscv' branch, got '$BASE_REF'"
+              exit 1
+            fi
+
+            BASE="$BASE_SHA"
+            HEAD="$HEAD_SHA"
+          else
+            echo "Push to riscv"
+            # 统一用 riscv 作为 baseline
+            git fetch origin riscv
+
+            BASE=$(git merge-base HEAD origin/main)
+            HEAD=$(git rev-parse HEAD)
+
+          fi
+
+          echo "BASE_COMMIT=$BASE" >> $GITHUB_ENV
+          echo "HEAD_COMMIT=$HEAD" >> $GITHUB_ENV
+
+          echo "Base: $BASE"
+          echo "Head: $HEAD"
+
+      - name: Generate patch
+        run: |
+          echo "Generating patch..."
+
+          git diff $BASE_COMMIT $HEAD_COMMIT > patch.diff
+
+          echo "Patch size:"
+          wc -l patch.diff
+          cat patch.diff
+
+          # 可选：避免空 patch
+          if [ ! -s patch.diff ]; then
+            echo "Warning: empty patch"
+          fi
+
+      - name: Trigger Jenkins Job
+        run: |
+          export BASE_COMMIT=${BASE_COMMIT}
+          export PATCH_FILE=$(pwd)/patch.diff
+          export GITHUB_PR=${PR_NUMBER:-0}
+
+          #bash /home/jenkins/scripts/jenkins-run.sh

From 98c8c8a024e728544598627dd68a63c7eaa33ce9 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Fri, 24 Apr 2026 14:58:31 +0800
Subject: [PATCH 03/21] Test ci with PR (#8)

* Add riscv64 ci with PR
---
 .github/workflows/ci-riscv64.yml | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index ffc859265b3c9..c14ce1e4c3efa 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -6,7 +6,6 @@ on:
 
   pull_request_target:
     types: [opened, synchronize, reopened]
-  
 
 name: CI (riscv64)
 
@@ -33,7 +32,7 @@ jobs:
       - name: Checkout repo
         uses: actions/checkout@v4
         with:
-          fetch-depth: 0   # merge-base
+          fetch-depth: 3000   # shadow clone?
 
       - name: Extract PR info
         run: |
@@ -44,7 +43,7 @@ jobs:
       - name: Diff base and head
         run: |
           if [ "${{ github.event_name }}" = "pull_request" ]; then
-          echo "Push PR build"
+            echo "Push PR build"
             BASE_REF="${{ github.base_ref }}"
             HEAD_REF="${{ github.head_ref }}"
 
@@ -57,8 +56,12 @@ jobs:
               exit 1
             fi
 
-            BASE="$BASE_SHA"
-            HEAD="$HEAD_SHA"
+            // need to get contents of the PR
+            git fetch origin pull/${{ github.event.pull_request.number }}/head:pr-head
+            git fetch origin pull/${{ github.event.pull_request.number }}/base:pr-base
+
+            BASE=$(git merge-base pr-base pr-head)
+            HEAD=pr-head
           else
             echo "Push to riscv"
             # 统一用 riscv 作为 baseline

From 26aab047a905057663918d956254208a6a1b15ea Mon Sep 17 00:00:00 2001
From: Bo YU <tsu.yubo@gmail.com>
Date: Fri, 24 Apr 2026 07:06:46 +0000
Subject: [PATCH 04/21] Fix no main brach issue
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

⭐ Run Main Diff base and head
Push to riscv
From https://github.com/RuyiAI-Stack/pytorch
 * branch              riscv      -> FETCH_HEAD
fatal: Not a valid object name origin/main
Error:   ❌  Failure - Main Diff base and head
Error: exit status 128
---
 .github/workflows/ci-riscv64.yml | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index c14ce1e4c3efa..3b3ddd23483e7 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -33,16 +33,16 @@ jobs:
         uses: actions/checkout@v4
         with:
           fetch-depth: 3000   # shadow clone?
+          ref: ${{ github.sha }} # including latest sha
 
       - name: Extract PR info
         run: |
           echo "BASE_SHA=${{ github.event.pull_request.base.sha }}" >> $GITHUB_ENV
           echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> GITHUB_ENV
-          echo "PR_NUMBER=${{ github.event.pull_request.number }}" >> GITHUB_ENV
-
+         
       - name: Diff base and head
         run: |
-          if [ "${{ github.event_name }}" = "pull_request" ]; then
+          if [[ "${{ github.event_name }}" = "pull_request" || "${{ github.event_name }}" == "pull_request_target" ]]; then
             echo "Push PR build"
             BASE_REF="${{ github.base_ref }}"
             HEAD_REF="${{ github.head_ref }}"
@@ -56,19 +56,19 @@ jobs:
               exit 1
             fi
 
-            // need to get contents of the PR
+            # need to get contents of the PR
             git fetch origin pull/${{ github.event.pull_request.number }}/head:pr-head
-            git fetch origin pull/${{ github.event.pull_request.number }}/base:pr-base
-
-            BASE=$(git merge-base pr-base pr-head)
+            git fetch origin main
+            BASE=$(git merge-base pr-head origin/main)
             HEAD=pr-head
           else
             echo "Push to riscv"
             # 统一用 riscv 作为 baseline
-            git fetch origin riscv
+            git fetch origin main
+            #git fetch origin riscv
 
-            BASE=$(git merge-base HEAD origin/main)
-            HEAD=$(git rev-parse HEAD)
+            BASE=$(git merge-base ${{ github.sha }} origin/main) # The latest commit
+            HEAD=${{ github.sha }}
 
           fi
 
@@ -97,6 +97,5 @@ jobs:
         run: |
           export BASE_COMMIT=${BASE_COMMIT}
           export PATCH_FILE=$(pwd)/patch.diff
-          export GITHUB_PR=${PR_NUMBER:-0}
 
-          #bash /home/jenkins/scripts/jenkins-run.sh
+          bash /home/jenkins/scripts/jenkins-run.sh

From 72843ab51037a67f5aa43264005bd62682c27691 Mon Sep 17 00:00:00 2001
From: Bo YU <tsu.yubo@gmail.com>
Date: Sat, 25 Apr 2026 14:21:06 +0000
Subject: [PATCH 05/21] move the patch to dest

---
 .github/workflows/ci-riscv64.yml | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index 3b3ddd23483e7..dec68a6d12c16 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -39,7 +39,7 @@ jobs:
         run: |
           echo "BASE_SHA=${{ github.event.pull_request.base.sha }}" >> $GITHUB_ENV
           echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> GITHUB_ENV
-         
+
       - name: Diff base and head
         run: |
           if [[ "${{ github.event_name }}" = "pull_request" || "${{ github.event_name }}" == "pull_request_target" ]]; then
@@ -82,20 +82,20 @@ jobs:
         run: |
           echo "Generating patch..."
 
-          git diff $BASE_COMMIT $HEAD_COMMIT > patch.diff
+          SHORT_HEAD=${HEAD_COMMIT:0:7}
+          PATCH_NAME="patch_${SHORT_HEAD}.patch"
+
+          git diff $BASE_COMMIT $HEAD_COMMIT > $PATCH_NAME
 
           echo "Patch size:"
-          wc -l patch.diff
-          cat patch.diff
+          wc -l $PATCH_NAME
 
-          # 可选：避免空 patch
-          if [ ! -s patch.diff ]; then
-            echo "Warning: empty patch"
-          fi
+          cp $PATCH_NAME /home/jenkins/patch/
+          cat /home/jenkins/patch/$PATCH_NAME
 
       - name: Trigger Jenkins Job
         run: |
           export BASE_COMMIT=${BASE_COMMIT}
           export PATCH_FILE=$(pwd)/patch.diff
 
-          bash /home/jenkins/scripts/jenkins-run.sh
+          #bash /home/jenkins/scripts/jenkins-run.sh

From 7338bc0422e101d7a183d4128b3fac93b78b3e44 Mon Sep 17 00:00:00 2001
From: XYenChi <oriachiuan@gmail.com>
Date: Mon, 27 Apr 2026 10:59:07 +0800
Subject: [PATCH 06/21] Fix block list format and remove
 test_cpu_select_algorithm (#4)

* mklnn is unavailable on RISC-V

* Remove test_cpu_select_algorithm from block_list

* Fix block list format
---
 test/inductor/test_cpu_select_algorithm.py |  2 +
 test/run_test.py                           | 52 +++++++++++-----------
 2 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/test/inductor/test_cpu_select_algorithm.py b/test/inductor/test_cpu_select_algorithm.py
index f35da9b6094d8..cdb7b3a95147f 100644
--- a/test/inductor/test_cpu_select_algorithm.py
+++ b/test/inductor/test_cpu_select_algorithm.py
@@ -1648,6 +1648,7 @@ def forward(self, x):
         vec_amx = VecAMX()
         self._check_amx_counter(vec_amx)
 
+    @unittest.skipIf(not torch._C._has_mkldnn, "MKLDNN is not enabled")
     @inductor_config.patch({"freezing": True})
     @patches
     @torch.no_grad
@@ -1766,6 +1767,7 @@ def forward(self, x, scale):
             vec_amx = VecAMX()
             self._check_amx_counter(vec_amx)
 
+    @unittest.skipIf(not torch._C._has_mkldnn, "MKLDNN is not enabled")
     @inductor_config.patch({"freezing": True, "cpp.enable_concat_linear": True})
     @patches
     @torch.no_grad
diff --git a/test/run_test.py b/test/run_test.py
index 45e64cd912960..a7bd7fbdbd6d9 100755
--- a/test/run_test.py
+++ b/test/run_test.py
@@ -298,40 +298,40 @@ def __contains__(self, item):
 
 RISCV64_BLOCKLIST = [
     # disable distributed related test
-    "inductor/test_distributed_patterns"
-    "fx/test_dce_pass"
-    "export/test_cpp_serdes"
-    "export/test_export"
-    "export/test_export_strict"
-    "export/test_export_training_ir_to_run_decomp"
-    "export/test_retraceability"
-    "export/test_serdes"
-    "export/test_strict_export_v2"
-    "test_public_bindings"
+    "inductor/test_distributed_patterns",
+    "fx/test_dce_pass",
+    "export/test_cpp_serdes",
+    "export/test_export",
+    "export/test_export_strict",
+    "export/test_export_training_ir_to_run_decomp",
+    "export/test_retraceability",
+    "export/test_serdes",
+    "export/test_strict_export_v2",
+    "test_public_bindings",
     # quantized engine NoQEngine is not supported
-    "test_torch"
-    "ao/sparsity/test_composability"
+    "test_torch",
+    "ao/sparsity/test_composability",
     # QNNPACK is not supported
-    "export/test_converter"
+    "export/test_converter",
     # record_contex_cpp is not support on non-linux non-x86_64 platforms
-    "torch_np/numpy_tests/core/test_numeric"
+    "torch_np/numpy_tests/core/test_numeric",
     # Failed to import torch.distributed.run: cannot import name 'Store' from 'torch.distributed'
-    "test_testing"
-    # TODO:L1 cache size = 0, need to fix
-    "inductor/test_cpu_select_algorithm"
-    "inductor/test_aot_inductor_arrayref"
-    "inductor/test_cpu_repro"
+    "test_testing",
+    "inductor/test_aot_inductor_arrayref",
+    "inductor/test_cpu_repro",
+    # TODO: mkldnn not available, shape guard failures on RISC-V
+    "inductor/test_cpu_select_algorithm",
     # TODO:scalar value not equal, need to fix
-    "profiler/test_profiler"
+    "profiler/test_profiler",
     # TODO precision
-    "test_binary_ufuncs"
-    "test_decomp"
+    "test_binary_ufuncs",
+    "test_decomp",
     # TODO no CUDA related module
-    "quantization/core/test_workflow_module"  # TestFakeQuantize.test_fq_module_per_channel
-    "quantization/core/test_workflow_ops"
-    "quantization/core/test_quantized_op"
+    "quantization/core/test_workflow_module",  # TestFakeQuantize.test_fq_module_per_channel
+    "quantization/core/test_workflow_ops",
+    "quantization/core/test_quantized_op",
     # z3-solver build fail
-    "test_proxy_tensor"
+    "test_proxy_tensor",
 ]
 
 

From 7444a799cf39d5c9046ef513057381410f61b476 Mon Sep 17 00:00:00 2001
From: Bo YU <tsu.yubo@gmail.com>
Date: Sat, 25 Apr 2026 14:21:06 +0000
Subject: [PATCH 07/21] move the patch to dest

---
 .github/workflows/ci-riscv64.yml | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index dec68a6d12c16..d8cd1ecdd8de3 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -57,14 +57,14 @@ jobs:
             fi
 
             # need to get contents of the PR
-            git fetch origin pull/${{ github.event.pull_request.number }}/head:pr-head
-            git fetch origin main
+            git fetch --quiet origin pull/${{ github.event.pull_request.number }}/head:pr-head
+            git fetch --quiet origin main
             BASE=$(git merge-base pr-head origin/main)
             HEAD=pr-head
           else
             echo "Push to riscv"
             # 统一用 riscv 作为 baseline
-            git fetch origin main
+            git fetch --quiet origin main
             #git fetch origin riscv
 
             BASE=$(git merge-base ${{ github.sha }} origin/main) # The latest commit
@@ -93,9 +93,8 @@ jobs:
           cp $PATCH_NAME /home/jenkins/patch/
           cat /home/jenkins/patch/$PATCH_NAME
 
+          echo "PATCH_FILE=$PATCH_NAME" >> $GITHUB_ENV
+
       - name: Trigger Jenkins Job
         run: |
-          export BASE_COMMIT=${BASE_COMMIT}
-          export PATCH_FILE=$(pwd)/patch.diff
-
-          #bash /home/jenkins/scripts/jenkins-run.sh
+          bash /home/jenkins/scripts/jenkins-run.sh $BASE_COMMIT  $PATCH_FILE

From c8cb84b5fd499213cd66fbf7311238418ef20930 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Sun, 3 May 2026 09:05:59 +0800
Subject: [PATCH 08/21] [blacklist]: update it (#11)

These cases are too slow on riscv64, adding them to here simply

Drop test_torch from the list because it is one core case
---
 test/run_test.py | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/test/run_test.py b/test/run_test.py
index a7bd7fbdbd6d9..f1363b7741963 100755
--- a/test/run_test.py
+++ b/test/run_test.py
@@ -308,8 +308,6 @@ def __contains__(self, item):
     "export/test_serdes",
     "export/test_strict_export_v2",
     "test_public_bindings",
-    # quantized engine NoQEngine is not supported
-    "test_torch",
     "ao/sparsity/test_composability",
     # QNNPACK is not supported
     "export/test_converter",
@@ -332,6 +330,15 @@ def __contains__(self, item):
     "quantization/core/test_quantized_op",
     # z3-solver build fail
     "test_proxy_tensor",
+    # too slow on riscv64
+    # 53013.55 s
+    "functorch/test_aotdispatch",
+    # 25069 s
+    "functorch/test_ops",
+    # 17528 s
+    "test_transformers",
+    # 10897 s
+    "functorch/test_vmap",
 ]
 
 

From abf25ccb035c4b3ac43be730a74a128aab2ca823 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Thu, 7 May 2026 12:32:52 +0800
Subject: [PATCH 09/21] Use commit sha on PR workflow (#12)

---
 .github/workflows/ci-riscv64.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index d8cd1ecdd8de3..44cd575a01e01 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -60,7 +60,7 @@ jobs:
             git fetch --quiet origin pull/${{ github.event.pull_request.number }}/head:pr-head
             git fetch --quiet origin main
             BASE=$(git merge-base pr-head origin/main)
-            HEAD=pr-head
+            HEAD=$(git rev-parse pr-head)
           else
             echo "Push to riscv"
             # 统一用 riscv 作为 baseline

From 930f39f629b9506295d62eed081fafcb3fc07a69 Mon Sep 17 00:00:00 2001
From: Yixuan Chen <chenyixuan@iscas.ac.cn>
Date: Sun, 26 Apr 2026 00:49:38 +0800
Subject: [PATCH 10/21] Fix bytes_to_scalar for float/complex on RISC-V

bytes_to_scalar previously round-tripped raw bytes through Python
float/complex values (via ctypes) before constructing the tensor. This
loses NaN bit patterns on architectures (such as RISC-V) that
canonicalize NaNs in floating-point loads/conversions, causing
test_bytes_to_scalar_cpu_{float32,float64,complex64,complex128} to
fail with mismatched storage bytes.

Construct the scalar tensor by writing the raw bytes directly into its
untyped storage so all input bit patterns (including NaN payloads) are
preserved exactly.
---
 torch/testing/_internal/common_utils.py | 37 +++++++++++--------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/torch/testing/_internal/common_utils.py b/torch/testing/_internal/common_utils.py
index eb65038aeef74..8e3a365855613 100644
--- a/torch/testing/_internal/common_utils.py
+++ b/torch/testing/_internal/common_utils.py
@@ -6034,27 +6034,22 @@ def check_bytes(byte_list):
             if not (0 <= byte <= 255):
                 raise AssertionError(f"byte value out of range: expected 0 <= byte <= 255, got {byte}")
 
-    if dtype.is_complex:
-        if len(byte_list) != (num_bytes * 2):
-            raise AssertionError(
-                f"expected len(byte_list) == {num_bytes * 2} for complex dtype, got {len(byte_list)}"
-            )
-        check_bytes(byte_list)
-        real = ctype.from_buffer((ctypes.c_byte * num_bytes)(
-            *byte_list[:num_bytes])).value
-        imag = ctype.from_buffer((ctypes.c_byte * num_bytes)(
-            *byte_list[num_bytes:])).value
-        res = real + 1j * imag
-    else:
-        if len(byte_list) != num_bytes:
-            raise AssertionError(
-                f"expected len(byte_list) == {num_bytes}, got {len(byte_list)}"
-            )
-        check_bytes(byte_list)
-        res = ctype.from_buffer((ctypes.c_byte * num_bytes)(
-            *byte_list)).value
-
-    return torch.tensor(res, device=device, dtype=dtype)
+    expected_len = num_bytes * 2 if dtype.is_complex else num_bytes
+    if len(byte_list) != expected_len:
+        raise AssertionError(
+            f"expected len(byte_list) == {expected_len}"
+            f"{' for complex dtype' if dtype.is_complex else ''}, got {len(byte_list)}"
+        )
+    check_bytes(byte_list)
+
+    # Write bytes directly into storage to preserve exact bit patterns
+    # (e.g. NaN payloads, which are not preserved when round-tripping through
+    # Python float/complex, especially on architectures like RISC-V that
+    # canonicalize NaNs).
+    res = torch.empty((), dtype=dtype, device=device)
+    src = torch.tensor(byte_list, dtype=torch.uint8, device=device)
+    res.untyped_storage().copy_(src.untyped_storage())
+    return res
 
 
 def copy_func(f):

From 782e92a75e8db8b61985310b89ec1860bc9688c3 Mon Sep 17 00:00:00 2001
From: Yixuan Chen <chenyixuan@iscas.ac.cn>
Date: Wed, 22 Apr 2026 15:27:45 +0800
Subject: [PATCH 11/21] Fix test_float_to_int_conversion_nonfinite for RISC-V

RISC-V converts non-finite floats to integers by saturating:
-inf -> min, inf/nan -> max for wider int types.
Add IS_RISCV64 flag and RISC-V-specific reference values.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
---
 test/test_tensor_creation_ops.py        | 8 ++++++++
 torch/testing/_internal/common_utils.py | 1 +
 2 files changed, 9 insertions(+)

diff --git a/test/test_tensor_creation_ops.py b/test/test_tensor_creation_ops.py
index fcaba5a15a558..fa93e7607077a 100644
--- a/test/test_tensor_creation_ops.py
+++ b/test/test_tensor_creation_ops.py
@@ -33,6 +33,7 @@
     IS_SANDCASTLE,
     IS_S390X,
     IS_ARM64,
+    IS_RISCV64,
     parametrize,
     TEST_WITH_TORCHDYNAMO,
     xfailIfTorchDynamo,
@@ -1127,6 +1128,13 @@ def test_float_to_int_conversion_nonfinite(self, device, dtype):
 
         if dtype == torch.bool:
             refs = (True, True, True)
+        elif IS_RISCV64:
+            if dtype in (torch.int32, torch.int64):
+                refs = (torch.iinfo(dtype).min, torch.iinfo(dtype).max, torch.iinfo(dtype).max)
+            elif dtype == torch.uint8:
+                refs = (0, torch.iinfo(dtype).max, torch.iinfo(dtype).max)
+            elif dtype in (torch.int8, torch.int16):
+                refs = (0, -1, -1)
         elif IS_ARM64:
             refs = (torch.iinfo(dtype).min, torch.iinfo(dtype).max, 0)
             if dtype in (torch.int8, torch.int16):
diff --git a/torch/testing/_internal/common_utils.py b/torch/testing/_internal/common_utils.py
index 8e3a365855613..5c87633309c64 100644
--- a/torch/testing/_internal/common_utils.py
+++ b/torch/testing/_internal/common_utils.py
@@ -1652,6 +1652,7 @@ def printErrors(self) -> None:
 IS_PPC = platform.machine() == "ppc64le"
 IS_X86 = platform.machine() in ('x86_64', 'i386')
 IS_ARM64 = platform.machine() in ('arm64', 'aarch64', 'ARM64')
+IS_RISCV64 = platform.machine() == 'riscv64'
 IS_S390X = platform.machine() == "s390x"
 IS_AVX512_VNNI_SUPPORTED = torch.cpu.get_capabilities().get("avx512_vnni", False)
 IS_CPU_EXT_SVE_SUPPORTED = torch.cpu.get_capabilities().get("sve", False)

From 12e0d7031fe47799a7ea1aa57357dc1048cceda8 Mon Sep 17 00:00:00 2001
From: Yixuan Chen <chenyixuan@iscas.ac.cn>
Date: Sat, 9 May 2026 15:59:22 +0800
Subject: [PATCH 12/21] Skip test if no qengine

---
 test/test_torch.py                      | 11 +++++++++--
 torch/testing/_internal/common_utils.py |  4 ++++
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/test/test_torch.py b/test/test_torch.py
index 805eed45b1aca..9c981ea895221 100644
--- a/test/test_torch.py
+++ b/test/test_torch.py
@@ -43,7 +43,7 @@
     wrapDeterministicFlagAPITest, DeterministicGuard, CudaSyncGuard,
     bytes_to_scalar, parametrize, noncontiguous_like,
     AlwaysWarnTypedStorageRemoval, TEST_WITH_TORCHDYNAMO, xfailIfTorchDynamo,
-    xfailIfS390X, set_warn_always_context, decorateIf, isRocmArchAnyOf,
+    xfailIfS390X, xfailIfRISCV, set_warn_always_context, decorateIf, isRocmArchAnyOf,
     IS_MACOS,
 )
 from multiprocessing.reduction import ForkingPickler
@@ -9852,14 +9852,21 @@ def test_type(self):
     # FIXME: port to a quantization test suite
     @unittest.skipIf(IS_MACOS, "https://github.com/pytorch/pytorch/issues/157245")
     @xfailIfS390X
+    @xfailIfRISCV
     def test_qengine(self):
         qengines = torch.backends.quantized.supported_engines
+        if not qengines:
+            self.skipTest("No quantized engines supported on this platform")
         original_qe = torch.backends.quantized.engine
         for qe in qengines:
             torch.backends.quantized.engine = qe
             if torch.backends.quantized.engine != qe:
                 raise AssertionError(f"qengine not set successfully: expected {qe}, got {torch.backends.quantized.engine}")
-        torch.backends.quantized.engine = original_qe
+        # On platforms where no qengine is compiled in as the default (e.g. RISC-V),
+        # the initial engine reads as "none" (NoQEngine), which is not a valid value
+        # to pass back to _set_qengine. Only restore if it was a real engine.
+        if original_qe != "none":
+            torch.backends.quantized.engine = original_qe
 
     def test_terminate_handler_on_crash(self):
         cmd = [sys.executable, '-c', "import os; os.environ[\"TORCH_CUSTOM_TERMINATE\"] ='1'; \
diff --git a/torch/testing/_internal/common_utils.py b/torch/testing/_internal/common_utils.py
index 5c87633309c64..8d130a7fe1463 100644
--- a/torch/testing/_internal/common_utils.py
+++ b/torch/testing/_internal/common_utils.py
@@ -1658,6 +1658,7 @@ def printErrors(self) -> None:
 IS_CPU_EXT_SVE_SUPPORTED = torch.cpu.get_capabilities().get("sve", False)
 IS_CPU_CAPABILITY_SVE = torch._C._get_cpu_capability() in ("SVE128", "SVE256")
 IS_CPU_CAPABILITY_SVE256 = torch._C._get_cpu_capability() == "SVE256"
+IS_RISCV = platform.machine() in ('riscv64', 'riscv32')
 
 if IS_WINDOWS:
     @contextmanager
@@ -2499,6 +2500,9 @@ def wrap_fn(self, *args, **kwargs):
 def xfailIfS390X(func):
     return unittest.expectedFailure(func) if IS_S390X else func
 
+def xfailIfRISCV(func):
+    return unittest.expectedFailure(func) if IS_RISCV else func
+
 def xfailIf(condition):
     def wrapper(func):
         if condition:

From 01db43b3c5ca3af0036fe92dce9b4a7af8f8d6fd Mon Sep 17 00:00:00 2001
From: XYenChi <oriachiuan@gmail.com>
Date: Wed, 20 May 2026 14:15:08 +0800
Subject: [PATCH 13/21] Replace offical cpuinfo repo (#18)

---
 .gitmodules | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitmodules b/.gitmodules
index 076ce38ac7938..35feb14cec9ae 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -41,7 +41,7 @@
 [submodule "third_party/cpuinfo"]
     ignore = dirty
     path = third_party/cpuinfo
-    url = https://github.com/pytorch/cpuinfo.git
+    url = https://github.com/RuyiAI-Stack/cpuinfo.git
 [submodule "third_party/python-peachpy"]
     ignore = dirty
     path = third_party/python-peachpy

From ddad2c3bab562c78be3da6f6fe5b2ac32f7c9c61 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Sun, 24 May 2026 23:34:18 +0800
Subject: [PATCH 14/21] [ci] split core and full ci (#20)

---
 .github/workflows/ci-riscv64.yml | 79 +++++++++++++++++++++++++++++---
 1 file changed, 72 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index 44cd575a01e01..127e0a01e36eb 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -1,5 +1,8 @@
 # Note: this runner is provided externally, so we minimize its access to
 # secrets.
+
+name: CI (riscv64)
+
 on:
   push:
     branches: [riscv]
@@ -7,8 +10,6 @@ on:
   pull_request_target:
     types: [opened, synchronize, reopened]
 
-name: CI (riscv64)
-
 permissions:
   contents: read
   # No permissions to secrets.
@@ -23,9 +24,17 @@ env:
   CARGO_TERM_COLOR: always
 
 jobs:
-  build:
-    name: Build and test
+  core-ci:
+    name: pytorch-riscv64-core-ci
     runs-on: [self-hosted, linux, amd64]
+
+    outputs:
+      base_commit: ${{ steps.meta.outputs.base_commit }}
+      head_commit: ${{ steps.meta.outputs.head_commit }}
+      patch_file: ${{ steps.patch.outputs.patch_file }}
+      ci_result_base_url: ${{ steps.jenkins.outputs.ci_result_base_url }}
+      ci_stat_url: ${{ steps.jenkins.outputs.ci_stat_url }}
+
     # This is in its own separate environment.
     environment: riscv64
     steps:
@@ -38,7 +47,7 @@ jobs:
       - name: Extract PR info
         run: |
           echo "BASE_SHA=${{ github.event.pull_request.base.sha }}" >> $GITHUB_ENV
-          echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> GITHUB_ENV
+          echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> $GITHUB_ENV
 
       - name: Diff base and head
         run: |
@@ -50,7 +59,7 @@ jobs:
             echo "Base ref: $BASE_REF"
             echo "Head ref: $HEAD_REF"
 
-            # 强约束: PR 必须基于 riscv
+            # must based on riscv
             if [ "$BASE_REF" != "riscv" ]; then
               echo "ERROR: PR must target 'riscv' branch, got '$BASE_REF'"
               exit 1
@@ -97,4 +106,60 @@ jobs:
 
       - name: Trigger Jenkins Job
         run: |
-          bash /home/jenkins/scripts/jenkins-run.sh $BASE_COMMIT  $PATCH_FILE
+          set -euo pipefail
+
+          BASE=${{ steps.meta.outputs.base_commit }}
+          PATCH=${{ steps.patch.outputs.patch_file }}
+
+          bash /home/jenkins/scripts/jenkins-run.sh $BASE_COMMIT  $PATCH_FILE | tee jenkins.log
+
+          CI_STAT_URL=$(grep -oE 'https://[^ ]+/pytorch-ci-stat\.json' jenkins.log | tail -n1)
+
+          if [[ -z "$CI_STAT_URL" ]]; then
+            echo "ERROR: cannot find pytorch-ci-stat.json URL from Jenkins log"
+            exit 1
+          fi
+
+          CI_RESULT_BASE_URL="${CI_STAT_URL%/pytorch-ci-stat.json}"
+
+          echo "ci_stat_url=$CI_STAT_URL" >> "$GITHUB_OUTPUT"
+          echo "ci_result_base_url=$CI_RESULT_BASE_URL" >> "$GITHUB_OUTPUT"
+
+          echo "CI_STAT_URL=$CI_STAT_URL"
+          echo "CI_RESULT_BASE_URL=$CI_RESULT_BASE_URL"
+
+full-ci:
+  name: pytorch-riscv64-full-ci
+  runs-on: [self-hosted, linux, amd64]
+  needs: core-ci
+  if: always()
+  continue-on-error: true
+
+  steps:
+    - name: Query existing full test result
+      shell: bash
+      run: |
+        set -euo pipefail
+
+        BASE_URL="${{ needs.core-ci.outputs.ci_result_base_url }}"
+        STAT_URL="${BASE_URL}/pytorch-ci-stat.json"
+
+        echo "STAT_URL=$STAT_URL"
+
+         curl -fsSL "$STAT_URL" -o pytorch-ci-stat.json
+
+        echo "==== FULL TEST STAT ===="
+        cat pytorch-ci-stat.json
+        echo
+
+        FAILED=$(jq '.failed | length' pytorch-ci-stat.json)
+
+        if [[ "$FAILED" != "0" ]]; then
+          echo "==== FULL TEST FAILED ===="
+          echo "failed cases: $FAILED"
+          exit 1
+        fi
+
+        echo "==== FULL TEST PASSED ===="
+        echo "full test no failures"
+

From 54a71e9a95f3cf079dadfa7ca09552fbd5248ea0 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Sun, 24 May 2026 23:51:12 +0800
Subject: [PATCH 15/21] [ci] fix ci workflow and other issue (#21)

for action, these yaml must be merged first then take effect, so merge
it skipping ci
---
 .github/workflows/ci-riscv64.yml | 63 ++++++++++++++++++--------------
 1 file changed, 35 insertions(+), 28 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index 127e0a01e36eb..8c53debb93a8e 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -50,6 +50,7 @@ jobs:
           echo "HEAD_SHA=${{ github.event.pull_request.head.sha }}" >> $GITHUB_ENV
 
       - name: Diff base and head
+        id: meta
         run: |
           if [[ "${{ github.event_name }}" = "pull_request" || "${{ github.event_name }}" == "pull_request_target" ]]; then
             echo "Push PR build"
@@ -84,10 +85,14 @@ jobs:
           echo "BASE_COMMIT=$BASE" >> $GITHUB_ENV
           echo "HEAD_COMMIT=$HEAD" >> $GITHUB_ENV
 
+          echo "base_commit=$BASE" >> "$GITHUB_OUTPUT"
+          echo "head_commit=$HEAD" >> "$GITHUB_OUTPUT"
+
           echo "Base: $BASE"
           echo "Head: $HEAD"
 
       - name: Generate patch
+        id: patch
         run: |
           echo "Generating patch..."
 
@@ -102,16 +107,18 @@ jobs:
           cp $PATCH_NAME /home/jenkins/patch/
           cat /home/jenkins/patch/$PATCH_NAME
 
-          echo "PATCH_FILE=$PATCH_NAME" >> $GITHUB_ENV
+          echo "PATCH_FILE=$PATCH_NAME" >> "$GITHUB_ENV"
+          echo "patch_file=$PATCH_NAME" >> "$GITHUB_OUTPUT"
 
       - name: Trigger Jenkins Job
+        id: jenkins
         run: |
           set -euo pipefail
 
           BASE=${{ steps.meta.outputs.base_commit }}
           PATCH=${{ steps.patch.outputs.patch_file }}
 
-          bash /home/jenkins/scripts/jenkins-run.sh $BASE_COMMIT  $PATCH_FILE | tee jenkins.log
+          bash /home/jenkins/scripts/jenkins-run.sh $BASE  $PATCH | tee jenkins.log
 
           CI_STAT_URL=$(grep -oE 'https://[^ ]+/pytorch-ci-stat\.json' jenkins.log | tail -n1)
 
@@ -128,38 +135,38 @@ jobs:
           echo "CI_STAT_URL=$CI_STAT_URL"
           echo "CI_RESULT_BASE_URL=$CI_RESULT_BASE_URL"
 
-full-ci:
-  name: pytorch-riscv64-full-ci
-  runs-on: [self-hosted, linux, amd64]
-  needs: core-ci
-  if: always()
-  continue-on-error: true
+  full-ci:
+    name: pytorch-riscv64-full-ci
+    runs-on: [self-hosted, linux, amd64]
+    needs: core-ci
+    if: always()
+    continue-on-error: true
 
-  steps:
-    - name: Query existing full test result
-      shell: bash
-      run: |
-        set -euo pipefail
+    steps:
+      - name: Query existing full test result
+        shell: bash
+        run: |
+          set -euo pipefail
 
-        BASE_URL="${{ needs.core-ci.outputs.ci_result_base_url }}"
-        STAT_URL="${BASE_URL}/pytorch-ci-stat.json"
+          BASE_URL="${{ needs.core-ci.outputs.ci_result_base_url }}"
+          STAT_URL="${BASE_URL}/pytorch-ci-stat.json"
 
-        echo "STAT_URL=$STAT_URL"
+          echo "STAT_URL=$STAT_URL"
 
-         curl -fsSL "$STAT_URL" -o pytorch-ci-stat.json
+          curl -fsSL "$STAT_URL" -o pytorch-ci-stat.json
 
-        echo "==== FULL TEST STAT ===="
-        cat pytorch-ci-stat.json
-        echo
+          echo "==== FULL TEST STAT ===="
+          cat pytorch-ci-stat.json
+          echo
 
-        FAILED=$(jq '.failed | length' pytorch-ci-stat.json)
+          FAILED=$(jq '.failed | length' pytorch-ci-stat.json)
 
-        if [[ "$FAILED" != "0" ]]; then
-          echo "==== FULL TEST FAILED ===="
-          echo "failed cases: $FAILED"
-          exit 1
-        fi
+          if [[ "$FAILED" != "0" ]]; then
+            echo "==== FULL TEST FAILED ===="
+            echo "failed cases: $FAILED"
+            exit 1
+          fi
 
-        echo "==== FULL TEST PASSED ===="
-        echo "full test no failures"
+          echo "==== FULL TEST PASSED ===="
+          echo "full test no failures"
 

From 2653522fc16a5b2385580f08c92f06cb155e8fe5 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Tue, 23 Jun 2026 21:33:42 +0800
Subject: [PATCH 16/21] [ci]: continue parsing Jenkins outputs after Jenkins
 job failure (#40)

---
 .github/workflows/ci-riscv64.yml | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index 8c53debb93a8e..f628f18b55c7a 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -118,13 +118,17 @@ jobs:
           BASE=${{ steps.meta.outputs.base_commit }}
           PATCH=${{ steps.patch.outputs.patch_file }}
 
+          set +e
           bash /home/jenkins/scripts/jenkins-run.sh $BASE  $PATCH | tee jenkins.log
+          JENKINS_RC=${PIPESTATUS[0]}
+          set -e
 
-          CI_STAT_URL=$(grep -oE 'https://[^ ]+/pytorch-ci-stat\.json' jenkins.log | tail -n1)
+          CI_STAT_URL=$(grep -oE 'https://[^ ]+/pytorch-ci-stat\.json' jenkins.log | tail -n1 || true)
 
           if [[ -z "$CI_STAT_URL" ]]; then
             echo "ERROR: cannot find pytorch-ci-stat.json URL from Jenkins log"
-            exit 1
+            echo "jenkins-run.sh rc=$JENKINS_RC"
+            exit "$JENKINS_RC"
           fi
 
           CI_RESULT_BASE_URL="${CI_STAT_URL%/pytorch-ci-stat.json}"
@@ -135,6 +139,9 @@ jobs:
           echo "CI_STAT_URL=$CI_STAT_URL"
           echo "CI_RESULT_BASE_URL=$CI_RESULT_BASE_URL"
 
+          # judge core ci fail or success
+          exit "$JENKINS_RC"
+
   full-ci:
     name: pytorch-riscv64-full-ci
     runs-on: [self-hosted, linux, amd64]

From 1571898a3c8d0d21968983381e44bba28c761c01 Mon Sep 17 00:00:00 2001
From: vimer <yuzibode@126.com>
Date: Wed, 22 Jul 2026 22:29:06 +0800
Subject: [PATCH 17/21] [CI] workaround to judge Jenkins job success (#41)

---
 .github/workflows/ci-riscv64.yml | 42 +++++++++++++++++++++++++++++---
 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/ci-riscv64.yml b/.github/workflows/ci-riscv64.yml
index f628f18b55c7a..85ea2d53fd102 100644
--- a/.github/workflows/ci-riscv64.yml
+++ b/.github/workflows/ci-riscv64.yml
@@ -110,13 +110,23 @@ jobs:
           echo "PATCH_FILE=$PATCH_NAME" >> "$GITHUB_ENV"
           echo "patch_file=$PATCH_NAME" >> "$GITHUB_OUTPUT"
 
-      - name: Trigger Jenkins Job
+      - name: Trigger Jenkins Job and get the CI results
         id: jenkins
         run: |
           set -euo pipefail
 
+          # Fail early if the runner does not provide the required tools.
+          for tool in curl jq; do
+            if ! command -v "$tool" >/dev/null 2>&1; then
+              echo "::error::Required command is unavailable: $tool"
+              exit 1
+            fi
+          done
+
           BASE=${{ steps.meta.outputs.base_commit }}
           PATCH=${{ steps.patch.outputs.patch_file }}
+          CORE_RESULT_FILE="$RUNNER_TEMP/pytorch-core-ci-stat.json"
+
 
           set +e
           bash /home/jenkins/scripts/jenkins-run.sh $BASE  $PATCH | tee jenkins.log
@@ -128,10 +138,11 @@ jobs:
           if [[ -z "$CI_STAT_URL" ]]; then
             echo "ERROR: cannot find pytorch-ci-stat.json URL from Jenkins log"
             echo "jenkins-run.sh rc=$JENKINS_RC"
-            exit "$JENKINS_RC"
+            exit 1
           fi
 
           CI_RESULT_BASE_URL="${CI_STAT_URL%/pytorch-ci-stat.json}"
+          CI_CORE_RESULT_URL="${CI_STAT_URL%/*}/pytorch-core-ci-stat.json"
 
           echo "ci_stat_url=$CI_STAT_URL" >> "$GITHUB_OUTPUT"
           echo "ci_result_base_url=$CI_RESULT_BASE_URL" >> "$GITHUB_OUTPUT"
@@ -139,8 +150,31 @@ jobs:
           echo "CI_STAT_URL=$CI_STAT_URL"
           echo "CI_RESULT_BASE_URL=$CI_RESULT_BASE_URL"
 
-          # judge core ci fail or success
-          exit "$JENKINS_RC"
+
+
+          if ! curl \
+            --fail \
+            --silent \
+            --show-error \
+            --location \
+            --retry 5 \
+           --retry-delay 5 \
+           --retry-connrefused \
+           --output "$CORE_RESULT_FILE" \
+           "$CI_CORE_RESULT_URL"; then
+           echo "::error::Failed to download $CI_CORE_RESULT_URL"
+           exit 1
+          fi
+
+          if jq -e '.failed == []' "$CORE_RESULT_FILE" >/dev/null; then
+            echo "Core CI succeeded: no failed tests"
+            exit 0
+          fi
+
+          echo "::error::Core CI reported failures"
+          echo "Failed tests:"
+          jq '.failed' "$CORE_RESULT_FILE" 2>/dev/null || cat "$CORE_RESULT_FILE"
+          exit 1
 
   full-ci:
     name: pytorch-riscv64-full-ci

From 5b326fe5d4982cb7c38d039a20ab5c70bf621c79 Mon Sep 17 00:00:00 2001
From: WuXintong123 <13683168028@163.com>
Date: Thu, 30 Jul 2026 10:30:39 +0800
Subject: [PATCH 18/21] [SyncBots] Integrate PyTorch at 1154a55

---
 torch/csrc/autograd/custom_function.cpp | 55 ++++++++++++++++++++++
 torch/csrc/autograd/custom_function.h   | 26 +++++++++++
 torch/testing/_internal/common_utils.py | 61 +++++++++++++++++++++++++
 3 files changed, 142 insertions(+)

diff --git a/torch/csrc/autograd/custom_function.cpp b/torch/csrc/autograd/custom_function.cpp
index 812e37cdf0766..643e06d6113b8 100644
--- a/torch/csrc/autograd/custom_function.cpp
+++ b/torch/csrc/autograd/custom_function.cpp
@@ -595,6 +595,61 @@ optional_variable_list _wrap_outputs(
       attached_node);
 }
 
+// Backward-compat 9-arg overloads (no attached_node out-param). Preserve the
+// pre-#189284 ABI so extensions compiled against a stale custom_function.h
+// still resolve _wrap_outputs at dlopen time. The dropped attached_node is
+// only needed to fire node-creation hooks; forwarding here silently discards
+// it, which is safe because callers that stopped at 9 args predate the hook.
+// NOLINTNEXTLINE(misc-use-internal-linkage)
+optional_variable_list _wrap_outputs(
+    const variable_list& input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view) {
+  c10::intrusive_ptr<Node> attached_node;
+  return _wrap_outputs_impl(
+      input_vars,
+      non_differentiable,
+      dirty_inputs,
+      raw_outputs,
+      cdata,
+      jvp_user_function,
+      to_save_if_setup_context,
+      view_as_self_fn,
+      pure_view,
+      attached_node);
+}
+
+// NOLINTNEXTLINE(misc-use-internal-linkage)
+optional_variable_list _wrap_outputs(
+    at::ArrayRef<const Variable*> input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view) {
+  c10::intrusive_ptr<Node> attached_node;
+  return _wrap_outputs_impl(
+      input_vars,
+      non_differentiable,
+      dirty_inputs,
+      raw_outputs,
+      cdata,
+      jvp_user_function,
+      to_save_if_setup_context,
+      view_as_self_fn,
+      pure_view,
+      attached_node);
+}
+
 void check_variable_result(
     const at::TensorBase& original,
     const at::TensorBase& result,
diff --git a/torch/csrc/autograd/custom_function.h b/torch/csrc/autograd/custom_function.h
index 62fb2986f03b4..3b805569e8c12 100644
--- a/torch/csrc/autograd/custom_function.h
+++ b/torch/csrc/autograd/custom_function.h
@@ -45,6 +45,32 @@ TORCH_API std::vector<std::optional<Variable>> _wrap_outputs(
     bool pure_view,
     c10::intrusive_ptr<Node>& attached_node);
 
+// Backward-compat overloads without the attached_node out-param. These match
+// the pre-#189284 ABI and let C++ extensions built against a stale header
+// still resolve _wrap_outputs at load time. Prefer the 10-arg versions above
+// for any new caller that needs to fire node creation hooks.
+TORCH_API std::vector<std::optional<Variable>> _wrap_outputs(
+    const variable_list& input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view);
+
+TORCH_API std::vector<std::optional<Variable>> _wrap_outputs(
+    at::ArrayRef<const Variable*> input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view);
+
 TORCH_API void check_variable_result(
     const at::TensorBase& original,
     const at::TensorBase& result,
diff --git a/torch/testing/_internal/common_utils.py b/torch/testing/_internal/common_utils.py
index 8d130a7fe1463..91e6205d86999 100644
--- a/torch/testing/_internal/common_utils.py
+++ b/torch/testing/_internal/common_utils.py
@@ -6575,12 +6575,73 @@ def install_cpp_extension(extension_root):
         sys.path.insert(0, mod_install_dir)
 
 
+# When torch/include on the build worker is stale from an install predating
+# upstream PR #189284, extensions compiled via load_inline see the old 9-arg
+# torch::autograd::_wrap_outputs declaration in custom_function.h and end up
+# with an undefined reference to that symbol at dlopen time. This stub, when
+# prepended to the extension's cpp_sources, provides a local definition of
+# the 9-arg overload that forwards to the 10-arg version already exported by
+# libtorch_cpu.so. Included unconditionally: on a fresh header, the 10-arg
+# call site wins overload resolution and this definition is unreferenced.
+_WRAP_OUTPUTS_ABI_SHIM = r"""
+namespace torch { namespace autograd {
+
+// Forward-declare the post-#189284 10-arg overload. libtorch_cpu.so always
+// exports this symbol, but pre-#189284 custom_function.h only declares the
+// 9-arg overload, so we redeclare it here to be able to call into it.
+extern std::vector<std::optional<Variable>> _wrap_outputs(
+    const variable_list& input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view,
+    c10::intrusive_ptr<Node>& attached_node);
+
+// Local definition of the pre-#189284 9-arg overload. The attached_node
+// out-param feeds node-creation hooks; discarding it here is safe because a
+// caller stuck on this ABI predates that feature and never fires hooks.
+inline std::vector<std::optional<Variable>> _wrap_outputs(
+    const variable_list& input_vars,
+    const std::unordered_set<at::TensorImpl*>& non_differentiable,
+    const std::unordered_set<at::TensorImpl*>& dirty_inputs,
+    const at::ArrayRef<std::optional<Variable>> raw_outputs,
+    const c10::intrusive_ptr<Node>& cdata,
+    const _jvp_fn_t& jvp_user_function,
+    const std::unordered_set<at::TensorImpl*>& to_save_if_setup_context,
+    const _view_as_self_fn_t& view_as_self_fn,
+    bool pure_view) {
+  c10::intrusive_ptr<Node> attached_node;
+  return _wrap_outputs(
+      input_vars, non_differentiable, dirty_inputs, raw_outputs, cdata,
+      jvp_user_function, to_save_if_setup_context, view_as_self_fn, pure_view,
+      attached_node);
+}
+
+}} // namespace torch::autograd
+"""
+
+
+def _inject_wrap_outputs_shim(kwargs):
+    sources = kwargs.get("cpp_sources")
+    if sources is None:
+        return
+    if isinstance(sources, str):
+        kwargs["cpp_sources"] = _WRAP_OUTPUTS_ABI_SHIM + sources
+    else:
+        kwargs["cpp_sources"] = [_WRAP_OUTPUTS_ABI_SHIM, *sources]
+
+
 # Decorator to provide a helper to load inline extensions to a temp directory
 def scoped_load_inline(func):
 
     @wraps(func)
     def wrapper(*args, **kwargs):
         def load_inline(*args, **kwargs):
+            _inject_wrap_outputs_shim(kwargs)
             if IS_WINDOWS:
                 # TODO(xmfan): even using TemporaryDirectoryName will result in permission error
                 return cpp_extension.load_inline(*args, **kwargs)

From 55d456eed361259964a26cb8a78549a77e73e2d3 Mon Sep 17 00:00:00 2001
From: WuXintong123 <13683168028@163.com>
Date: Wed, 12 Aug 2026 09:26:08 +0800
Subject: [PATCH 19/21] [SyncBots] Integrate PyTorch at 2760264

---
 test/test_nn.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test/test_nn.py b/test/test_nn.py
index afec5193df99f..d4242ec99d11e 100644
--- a/test/test_nn.py
+++ b/test/test_nn.py
@@ -13799,7 +13799,7 @@ def _test_linear_cross_entropy_loss(self, device='cpu', dtype=torch.float32,
             expected_max_ulp_diff = 8
             if dtype == torch.float32:
                 if "cpu" in device:
-                    expected_input_grad_max_ulp_diff = 384  # x86_64 149
+                    expected_input_grad_max_ulp_diff = 512  # x86_64 149, ci 426
                     expected_weight_grad_max_ulp_diff = 160  # x86_64 58
                 elif "mps" in device:
                     expected_input_grad_max_ulp_diff = 128  # 37

From 6e72cda72e25c4bd67429bec460a7c7cc1922433 Mon Sep 17 00:00:00 2001
From: Wu Xintong <13683168028@163.com>
Date: Wed, 12 Aug 2026 22:38:57 +0800
Subject: [PATCH 20/21] [test]Scope linear cross entropy ULP tolerance to
 RISC-V (#42)

---
 test/test_nn.py | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/test/test_nn.py b/test/test_nn.py
index d4242ec99d11e..45ffde2d64955 100644
--- a/test/test_nn.py
+++ b/test/test_nn.py
@@ -37,7 +37,7 @@
 from torch.testing._internal.common_utils import dtype_name, freeze_rng_state, run_tests, TestCase, \
     skipIfNoLapack, skipIfRocm, skipIfRocmVersionLessThan, getRocmVersion, TEST_NUMPY, TEST_SCIPY, TEST_WITH_CROSSREF, TEST_WITH_ROCM, TEST_MULTIACCELERATOR, \
     download_file, get_function_arglist, load_tests, skipIfMPS, MACOS_VERSION, \
-    IS_PPC, IS_ARM64, IS_MACOS, IS_WINDOWS, IS_CPU_CAPABILITY_SVE, IS_CPU_EXT_SVE_SUPPORTED, xfailIf, \
+    IS_PPC, IS_ARM64, IS_RISCV64, IS_MACOS, IS_WINDOWS, IS_CPU_CAPABILITY_SVE, IS_CPU_EXT_SVE_SUPPORTED, xfailIf, \
     parametrize as parametrize_test, subtest, instantiate_parametrized_tests, \
     skipIfTorchDynamo, gcIfJetson, set_default_dtype, skipIfNoCuteDSL, isRocmArchAnyOf, MI200_ARCH
 from torch.testing._internal.common_cuda import TEST_CUDA, TEST_CUDNN, \
@@ -13799,7 +13799,10 @@ def _test_linear_cross_entropy_loss(self, device='cpu', dtype=torch.float32,
             expected_max_ulp_diff = 8
             if dtype == torch.float32:
                 if "cpu" in device:
-                    expected_input_grad_max_ulp_diff = 512  # x86_64 149, ci 426
+                    if IS_RISCV64:
+                        expected_input_grad_max_ulp_diff = 512  # riscv64 426
+                    else:
+                        expected_input_grad_max_ulp_diff = 384  # x86_64 149
                     expected_weight_grad_max_ulp_diff = 160  # x86_64 58
                 elif "mps" in device:
                     expected_input_grad_max_ulp_diff = 128  # 37

From 91cc85c7a22c6841763521e110f2339b35e5d056 Mon Sep 17 00:00:00 2001
From: Sherlockzhangjinge <zjgzhangjinge@outlook.com>
Date: Mon, 31 Aug 2026 13:13:30 +0800
Subject: [PATCH 21/21] RISC-V Vector Extension (RVV) support for ATen

Signed-off-by: Fei Zhang <zhangfei@iscas.ac.cn>
Co-authored-by: Chung-Lin Tang <cltang@baylibre.com>
---
 aten/src/ATen/CMakeLists.txt               |   2 +-
 aten/src/ATen/Version.cpp                  |   3 +
 aten/src/ATen/cpu/vec/rvv/rvv_helper.h     |  26 +
 aten/src/ATen/cpu/vec/rvv/vec_bfloat16.h   | 126 ++++
 aten/src/ATen/cpu/vec/rvv/vec_common_rvv.h |  14 +
 aten/src/ATen/cpu/vec/rvv/vec_float.h      | 702 +++++++++++++++++++++
 aten/src/ATen/cpu/vec/rvv/vec_qint32.h     | 167 +++++
 aten/src/ATen/cpu/vec/rvv/vec_qint8.h      | 340 ++++++++++
 aten/src/ATen/cpu/vec/rvv/vec_quint8.h     | 367 +++++++++++
 aten/src/ATen/cpu/vec/vec256/vec256.h      |   4 +-
 aten/src/ATen/cpu/vec/vec_base.h           |  11 +
 aten/src/ATen/native/DispatchStub.cpp      |  39 ++
 aten/src/ATen/native/DispatchStub.h        |  32 +-
 aten/src/ATen/native/cpu/LerpKernel.cpp    |   2 +-
 aten/src/ATen/test/vec_test_all_types.cpp  |   2 +-
 aten/src/ATen/test/vec_test_all_types.h    |   2 +-
 cmake/Codegen.cmake                        |   6 +
 cmake/Dependencies.cmake                   |   2 +
 cmake/Modules/FindRVV.cmake                |  61 ++
 torch/backends/cpu/__init__.py             |   1 +
 torch/headeronly/cpu/vec/intrinsics.h      |   2 +
 21 files changed, 1905 insertions(+), 6 deletions(-)
 create mode 100644 aten/src/ATen/cpu/vec/rvv/rvv_helper.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_bfloat16.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_common_rvv.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_float.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_qint32.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_qint8.h
 create mode 100644 aten/src/ATen/cpu/vec/rvv/vec_quint8.h
 create mode 100644 cmake/Modules/FindRVV.cmake

diff --git a/aten/src/ATen/CMakeLists.txt b/aten/src/ATen/CMakeLists.txt
index 0a09960a70950..481768ced7d00 100644
--- a/aten/src/ATen/CMakeLists.txt
+++ b/aten/src/ATen/CMakeLists.txt
@@ -74,7 +74,7 @@ if(NOT BUILD_LITE_INTERPRETER)
 endif()
 EXCLUDE(ATen_CORE_SRCS "${ATen_CORE_SRCS}" ${ATen_CORE_TEST_SRCS})
 
-file(GLOB base_h CONFIGURE_DEPENDS "*.h" "detail/*.h" "cpu/*.h" "cpu/vec/vec512/*.h" "cpu/vec/vec128/*.h" "cpu/vec/vec256/*.h" "cpu/vec/vec256/vsx/*.h" "cpu/vec/vec256/zarch/*.h" "cpu/vec/sve/*.h" "cpu/vec/*.h" "quantized/*.h" "functorch/*.h" "accelerator/*.h")
+file(GLOB base_h CONFIGURE_DEPENDS "*.h" "detail/*.h" "cpu/*.h" "cpu/vec/vec512/*.h" "cpu/vec/vec128/*.h" "cpu/vec/vec256/*.h" "cpu/vec/vec256/vsx/*.h" "cpu/vec/vec256/zarch/*.h" "cpu/vec/sve/*.h" "cpu/vec/rvv/*.h" "cpu/vec/*.h" "quantized/*.h" "functorch/*.h" "accelerator/*.h")
 file(GLOB base_cpp CONFIGURE_DEPENDS "*.cpp" "detail/*.cpp" "cpu/*.cpp" "functorch/*.cpp" "accelerator/*.cpp")
 file(GLOB cuda_h CONFIGURE_DEPENDS "cuda/*.h" "cuda/detail/*.h" "cuda/*.cuh" "cuda/detail/*.cuh" "cuda/tunable/*.cuh" "cuda/tunable/*.h")
 file(GLOB cuda_cpp CONFIGURE_DEPENDS "cuda/*.cpp" "cuda/detail/*.cpp" "cuda/tunable/*.cpp")
diff --git a/aten/src/ATen/Version.cpp b/aten/src/ATen/Version.cpp
index 53a43985bbd98..dc1c904e9dac2 100644
--- a/aten/src/ATen/Version.cpp
+++ b/aten/src/ATen/Version.cpp
@@ -107,6 +107,9 @@ std::string get_cpu_capability() {
       return "SVE128";
     case native::CPUCapability::SVE256:
       return "SVE256";
+#elif defined(HAVE_RVV_CPU_DEFINITION)
+    case native::CPUCapability::RVV:
+      return "RVV";
 #else
     case native::CPUCapability::AVX2:
       return "AVX2";
diff --git a/aten/src/ATen/cpu/vec/rvv/rvv_helper.h b/aten/src/ATen/cpu/vec/rvv/rvv_helper.h
new file mode 100644
index 0000000000000..9179a0f440371
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/rvv_helper.h
@@ -0,0 +1,26 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/vec_base.h>
+
+#if defined(CPU_CAPABILITY_RVV)
+
+typedef int8_t fixed_vint8m2_t[CONFIG_VLMAX / sizeof(int8_t)];
+typedef int16_t fixed_vint16m2_t[CONFIG_VLMAX / sizeof(int16_t)];
+typedef int32_t fixed_vint32m2_t[CONFIG_VLMAX / sizeof(int32_t)];
+typedef int64_t fixed_vint64m2_t[CONFIG_VLMAX / sizeof(int64_t)];
+
+typedef uint8_t fixed_vuint8m2_t[CONFIG_VLMAX / sizeof(uint8_t)];
+typedef uint16_t fixed_vuint16m2_t[CONFIG_VLMAX / sizeof(uint16_t)];
+typedef uint32_t fixed_vuint32m2_t[CONFIG_VLMAX / sizeof(uint32_t)];
+typedef uint64_t fixed_vuint64m2_t[CONFIG_VLMAX / sizeof(uint64_t)];
+
+typedef float fixed_vfloat32m2_t[CONFIG_VLMAX / sizeof(float)];
+typedef double fixed_vfloat64m2_t[CONFIG_VLMAX / sizeof(double)];
+
+#define VFLOAT32_VL (CONFIG_VLMAX_BITS / 32)
+#define VQINT8_VL (CONFIG_VLMAX_BITS / 8)
+#define VQUINT8_VL (CONFIG_VLMAX_BITS / 8)
+#define VQINT32_VL (CONFIG_VLMAX_BITS / 32)
+
+#endif // defined(CPU_CAPABILITY_RVV)
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_bfloat16.h b/aten/src/ATen/cpu/vec/rvv/vec_bfloat16.h
new file mode 100644
index 0000000000000..0998d6e937eab
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_bfloat16.h
@@ -0,0 +1,126 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/vec_base.h>
+#include <c10/util/irange.h>
+
+namespace at {
+namespace vec {
+// See Note [CPU_CAPABILITY namespace]
+inline namespace CPU_CAPABILITY {
+
+// Generic implementation
+//  TO-DO : Add Zvfbfmin for rvv
+inline std::tuple<Vectorized<float>, Vectorized<float>> convert_bfloat16_float(
+    const Vectorized<BFloat16>& a) {
+  constexpr int64_t K = Vectorized<BFloat16>::size();
+  __at_align__ float arr[K];
+  __at_align__ BFloat16 arr2[K];
+  a.store(arr2);
+  convert(arr2, arr, K);
+  return std::make_tuple(
+      Vectorized<float>::loadu(arr),
+      Vectorized<float>::loadu(arr + Vectorized<float>::size()));
+}
+
+inline Vectorized<BFloat16> convert_float_bfloat16(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  constexpr int64_t K = Vectorized<BFloat16>::size();
+  __at_align__ float arr[K];
+  __at_align__ BFloat16 arr2[K];
+  a.store(arr);
+  b.store(arr + Vectorized<float>::size());
+  convert(arr, arr2, K);
+  return Vectorized<BFloat16>::loadu(arr2);
+}
+
+// Generic implementation
+// TO-DO : Add Zvfhmin for rvv
+inline std::tuple<Vectorized<float>, Vectorized<float>> convert_half_float(
+    const Vectorized<Half>& a) {
+  constexpr int64_t K = Vectorized<Half>::size();
+  __at_align__ float arr[K];
+  __at_align__ Half arr2[K];
+  a.store(arr2);
+  convert(arr2, arr, K);
+  return std::make_tuple(
+      Vectorized<float>::loadu(arr),
+      Vectorized<float>::loadu(arr + Vectorized<float>::size()));
+}
+
+inline Vectorized<Half> convert_float_half(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  constexpr int64_t K = Vectorized<Half>::size();
+  __at_align__ float arr[K];
+  __at_align__ Half arr2[K];
+  a.store(arr);
+  b.store(arr + Vectorized<float>::size());
+  convert(arr, arr2, K);
+  return Vectorized<Half>::loadu(arr2);
+};
+
+template <>
+inline Vectorized<Half> fmadd(
+    const Vectorized<Half>& a,
+    const Vectorized<Half>& b,
+    const Vectorized<Half>& c) {
+  const auto [a0, a1] = convert_half_float(a);
+  const auto [b0, b1] = convert_half_float(b);
+  const auto [c0, c1] = convert_half_float(c);
+  return convert_float_half(
+      at::vec::fmadd(a0, b0, c0), at::vec::fmadd(a1, b1, c1));
+}
+
+template <>
+inline Vectorized<Half> fmsub(
+    const Vectorized<Half>& a,
+    const Vectorized<Half>& b,
+    const Vectorized<Half>& c) {
+  const auto [a0, a1] = convert_half_float(a);
+  const auto [b0, b1] = convert_half_float(b);
+  const auto [c0, c1] = convert_half_float(c);
+  return convert_float_half(
+      at::vec::fmsub(a0, b0, c0), at::vec::fmsub(a1, b1, c1));
+}
+
+inline void load_fp32_from_bf16(
+    const c10::BFloat16* data,
+    Vectorized<float>& out) {
+  __at_align__ float values[Vectorized<float>::size()];
+  for (const auto k : c10::irange(Vectorized<float>::size())) {
+    values[k] = data[k];
+  }
+  out = Vectorized<float>::loadu(values);
+}
+
+inline void load_fp32_from_bf16(
+    const c10::BFloat16* data,
+    Vectorized<float>& out1,
+    Vectorized<float>& out2) {
+  load_fp32_from_bf16(data, out1);
+  data += Vectorized<float>::size();
+  load_fp32_from_bf16(data, out2);
+}
+
+inline void load_fp32_from_fp16(const c10::Half* data, Vectorized<float>& out) {
+  __at_align__ float values[Vectorized<float>::size()];
+  for (const auto k : c10::irange(Vectorized<float>::size())) {
+    values[k] = data[k];
+  }
+  out = Vectorized<float>::loadu(values);
+}
+
+inline void load_fp32_from_fp16(
+    const c10::Half* data,
+    Vectorized<float>& out1,
+    Vectorized<float>& out2) {
+  load_fp32_from_fp16(data, out1);
+  data += Vectorized<float>::size();
+  load_fp32_from_fp16(data, out2);
+}
+
+} // namespace CPU_CAPABILITY
+} // namespace vec
+} // namespace at
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_common_rvv.h b/aten/src/ATen/cpu/vec/rvv/vec_common_rvv.h
new file mode 100644
index 0000000000000..085b82129bd23
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_common_rvv.h
@@ -0,0 +1,14 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+
+#include <ATen/cpu/vec/rvv/rvv_helper.h>
+#include <ATen/cpu/vec/vec_base.h>
+
+#if defined(CPU_CAPABILITY_RVV)
+#include <ATen/cpu/vec/rvv/vec_float.h>
+#include <ATen/cpu/vec/rvv/vec_qint32.h>
+#include <ATen/cpu/vec/rvv/vec_qint8.h>
+#include <ATen/cpu/vec/rvv/vec_quint8.h>
+#include <ATen/cpu/vec/rvv/vec_bfloat16.h>
+#endif
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_float.h b/aten/src/ATen/cpu/vec/rvv/vec_float.h
new file mode 100644
index 0000000000000..b477830e29826
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_float.h
@@ -0,0 +1,702 @@
+#pragma once
+
+// DO NOT DEFINE STATIC DATA IN THIS HEADER!
+// See Note [Do not compile initializers with AVX]
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/rvv/rvv_helper.h>
+#include <ATen/cpu/vec/vec_base.h>
+#include <c10/util/irange.h>
+
+#include <sleef.h>
+#include <cstdint>
+
+namespace at::vec {
+inline namespace CPU_CAPABILITY {
+
+template <>
+class Vectorized<float> {
+ private:
+  fixed_vfloat32m2_t values;
+
+ public:
+  using value_type = float;
+  using size_type = int;
+  static constexpr size_type size() {
+    return VFLOAT32_VL;
+  }
+  Vectorized() {}
+  Vectorized(vfloat32m2_t v) {
+    __riscv_vse32_v_f32m2(values, v, VFLOAT32_VL);
+  }
+  Vectorized(float val) {
+    vfloat32m2_t v = __riscv_vfmv_v_f_f32m2(val, VFLOAT32_VL);
+    __riscv_vse32_v_f32m2(values, v, VFLOAT32_VL);
+  }
+  Vectorized(
+      float val0,
+      float val1,
+      float val2,
+      float val3,
+      float val4,
+      float val5,
+      float val6,
+      float val7) {
+    values[0] = val0;
+    values[1] = val1;
+    values[2] = val2;
+    values[3] = val3;
+    values[4] = val4;
+    values[5] = val5;
+    values[6] = val6;
+    values[7] = val7;
+  }
+
+  operator vfloat32m2_t() const {
+    return __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+  }
+
+  template <int64_t mask>
+  static Vectorized<float> blend(
+      const Vectorized<float>& a,
+      const Vectorized<float>& b) {
+    vint64m1_t mask_vec = __riscv_vmv_v_x_i64m1(mask, 1);
+    vbool16_t bool_vec = __riscv_vreinterpret_v_i64m1_b16(mask_vec);
+    vfloat32m2_t a_values = __riscv_vle32_v_f32m2(a.values, VFLOAT32_VL);
+    vfloat32m2_t b_values = __riscv_vle32_v_f32m2(b.values, VFLOAT32_VL);
+    return __riscv_vmerge_vvm_f32m2(a_values, b_values, bool_vec, VFLOAT32_VL);
+  }
+
+  static Vectorized<float> blendv(
+      const Vectorized<float>& a,
+      const Vectorized<float>& b,
+      const Vectorized<float>& mask) {
+    vfloat32m2_t mask_values = __riscv_vle32_v_f32m2(mask.values, VFLOAT32_VL);
+    vuint32m2_t mask_u32 = __riscv_vreinterpret_v_f32m2_u32m2(mask_values);
+    vuint32m2_t and_u32 = __riscv_vand_vx_u32m2(mask_u32, 0x01, VFLOAT32_VL);
+    vbool16_t bool_vec = __riscv_vmseq_vx_u32m2_b16(and_u32, 0x01, VFLOAT32_VL);
+    vfloat32m2_t a_values = __riscv_vle32_v_f32m2(a.values, VFLOAT32_VL);
+    vfloat32m2_t b_values = __riscv_vle32_v_f32m2(b.values, VFLOAT32_VL);
+    return __riscv_vmerge_vvm_f32m2(a_values, b_values, bool_vec, VFLOAT32_VL);
+  }
+
+  template <typename step_t>
+  static Vectorized<float> arange(
+      float base = 0.f,
+      step_t step = static_cast<step_t>(1)) {
+    const Vectorized<float> base_vec(base);
+    const Vectorized<float> step_vec(step);
+    const Vectorized<float> step_sizes(0, 1, 2, 3, 4, 5, 6, 7);
+    return fmadd(step_sizes, step_vec, base_vec);
+  }
+
+  static Vectorized<float> set(
+      const Vectorized<float>& a,
+      const Vectorized<float>& b,
+      size_t count = size()) {
+    switch (count) {
+      case 0:
+        return a;
+      case 1:
+        return blend<1>(a, b);
+      case 2:
+        return blend<3>(a, b);
+      case 3:
+        return blend<7>(a, b);
+      case 4:
+        return blend<15>(a, b);
+      case 5:
+        return blend<31>(a, b);
+      case 6:
+        return blend<63>(a, b);
+      case 7:
+        return blend<127>(a, b);
+    }
+
+    return b;
+  }
+
+  static Vectorized<float> loadu(const void* ptr, int64_t count = size()) {
+#ifdef RVV_SUPPORT_UNALIGN
+    if (count == size()) {
+      return __riscv_vle32_v_f32m2(
+          reinterpret_cast<const float*>(ptr), VFLOAT32_VL);
+    } else {
+      vfloat32m2_t zero_vec = __riscv_vfmv_v_f_f32m2(0.f, VFLOAT32_VL);
+      return __riscv_vle32_v_f32m2_tu(
+          zero_vec, reinterpret_cast<const float*>(ptr), count);
+    }
+#else
+    // If the address of ptr is not aligned, the performance will be very slow.
+    if (reinterpret_cast<uintptr_t>(ptr) & 0x3) {
+      __at_align__ float tmp_values[size()];
+      for (const auto i : c10::irange(size())) {
+        tmp_values[i] = 0.0;
+      }
+      std::memcpy(
+          tmp_values,
+          reinterpret_cast<const float*>(ptr),
+          count * sizeof(float));
+      return __riscv_vle32_v_f32m2(tmp_values, VFLOAT32_VL);
+    } else {
+      if (count == size()) {
+        return __riscv_vle32_v_f32m2(
+            reinterpret_cast<const float*>(ptr), VFLOAT32_VL);
+      } else {
+        vfloat32m2_t zero_vec = __riscv_vfmv_v_f_f32m2(0.f, VFLOAT32_VL);
+        return __riscv_vle32_v_f32m2_tu(
+            zero_vec, reinterpret_cast<const float*>(ptr), count);
+      }
+    }
+#endif
+  }
+
+  void store(void* ptr, int64_t count = size()) const {
+    std::memcpy(ptr, this->values, count * sizeof(float));
+  }
+
+  const float& operator[](int idx) const = delete;
+  float& operator[](int idx) = delete;
+
+  int zero_mask() const {
+    __at_align__ float tmp[size()];
+    store(tmp);
+    int mask = 0;
+    for (int i = 0; i < size(); ++i) {
+      if (tmp[i] == 0.f) {
+        mask |= (1 << i);
+      }
+    }
+    return mask;
+  }
+
+  Vectorized<float> isnan() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vuint32m2_t classify = __riscv_vfclass_v_u32m2(values, VFLOAT32_VL);
+    vbool16_t isSNaN = __riscv_vmseq_vx_u32m2_b16(classify, 0x100, VFLOAT32_VL);
+    vbool16_t isQNaN = __riscv_vmseq_vx_u32m2_b16(classify, 0x200, VFLOAT32_VL);
+    vbool16_t isNaN = __riscv_vmor_mm_b16(isSNaN, isQNaN, VFLOAT32_VL);
+    vuint32m2_t zero_vec = __riscv_vmv_v_x_u32m2(0, VFLOAT32_VL);
+    vuint32m2_t vec_u32 =
+        __riscv_vmerge_vxm_u32m2(zero_vec, 0xFFFFFFFF, isNaN, VFLOAT32_VL);
+    return __riscv_vreinterpret_v_u32m2_f32m2(vec_u32);
+  }
+
+  bool has_inf_nan() const {
+    __at_align__ float tmp[size()];
+    store(tmp);
+    for (const auto i : c10::irange(size())) {
+      if (_isnan(tmp[i]) || _isinf(tmp[i])) {
+        return true;
+      }
+    }
+    return false;
+  }
+
+  Vectorized<float> map(float (*const f)(float)) const {
+    __at_align__ float tmp[size()];
+    store(tmp);
+    for (const auto i : c10::irange(size())) {
+      tmp[i] = f(tmp[i]);
+    }
+    return loadu(tmp);
+  }
+
+  Vectorized<float> abs() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(__riscv_vfabs_v_f32m2(values, VFLOAT32_VL));
+  }
+  Vectorized<float> angle() const {
+    auto zero = Vectorized<float>(0);
+    auto pi = Vectorized<float>(c10::pi<float>);
+    auto tmp = blendv(zero, pi, *this < zero);
+    return blendv(tmp, *this, isnan());
+  }
+  Vectorized<float> real() const {
+    return *this;
+  }
+  Vectorized<float> imag() const {
+    return Vectorized<float>(0.f);
+  }
+  Vectorized<float> conj() const {
+    return *this;
+  }
+  Vectorized<float> acos() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_acosfx_u10rvvm2(values));
+  }
+  Vectorized<float> acosh() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_acoshfx_u10rvvm2(values));
+  }
+  Vectorized<float> asin() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_asinfx_u10rvvm2(values));
+  }
+  Vectorized<float> atan() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_atanfx_u10rvvm2(values));
+  }
+  Vectorized<float> atanh() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_atanhfx_u10rvvm2(values));
+  }
+  Vectorized<float> atan2(const Vectorized<float>& exp) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(exp.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_atan2fx_u10rvvm2(a, b));
+  }
+  Vectorized<float> copysign(const Vectorized<float>& sign) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(sign.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_copysignfx_rvvm2(a, b));
+  }
+  Vectorized<float> erf() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_erffx_u10rvvm2(values));
+  }
+  Vectorized<float> erfc() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_erfcfx_u15rvvm2(values));
+  }
+  Vectorized<float> erfinv() const {
+    return map(calc_erfinv);
+  }
+  Vectorized<float> exp() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_expfx_u10rvvm2(values));
+  }
+  Vectorized<float> exp2() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_exp2fx_u10rvvm2(values));
+  }
+  Vectorized<float> expm1() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_expm1fx_u10rvvm2(values));
+  }
+  Vectorized<float> exp_u20() const {
+    return exp();
+  }
+  Vectorized<float> fexp_u20() const {
+    return exp();
+  }
+  Vectorized<float> fmod(const Vectorized<float>& q) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(q.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_fmodfx_rvvm2(a, b));
+  }
+  Vectorized<float> hypot(const Vectorized<float>& b) const {
+    vfloat32m2_t x = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t y = __riscv_vle32_v_f32m2(b.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_hypotfx_u05rvvm2(x, y));
+  }
+  Vectorized<float> i0() const {
+    return map(calc_i0);
+  }
+  Vectorized<float> i0e() const {
+    return map(calc_i0e);
+  }
+  Vectorized<float> digamma() const {
+    return map(calc_digamma);
+  }
+  Vectorized<float> igamma(const Vectorized<float>& x) const {
+    __at_align__ float tmp[size()];
+    __at_align__ float tmp_x[size()];
+    store(tmp);
+    x.store(tmp_x);
+    for (const auto i : c10::irange(size())) {
+      tmp[i] = calc_igamma(tmp[i], tmp_x[i]);
+    }
+    return loadu(tmp);
+  }
+  Vectorized<float> igammac(const Vectorized<float>& x) const {
+    __at_align__ float tmp[size()];
+    __at_align__ float tmp_x[size()];
+    store(tmp);
+    x.store(tmp_x);
+    for (const auto i : c10::irange(size())) {
+      tmp[i] = calc_igammac(tmp[i], tmp_x[i]);
+    }
+    return loadu(tmp);
+  }
+  Vectorized<float> log() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_logfx_u10rvvm2(values));
+  }
+  Vectorized<float> log10() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_log10fx_u10rvvm2(values));
+  }
+  Vectorized<float> log1p() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_log1pfx_u10rvvm2(values));
+  }
+  Vectorized<float> log2() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_log2fx_u10rvvm2(values));
+  }
+  Vectorized<float> nextafter(const Vectorized<float>& b) const {
+    vfloat32m2_t x = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t y = __riscv_vle32_v_f32m2(b.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_nextafterfx_rvvm2(x, y));
+  }
+  Vectorized<float> frac() const;
+  Vectorized<float> sin() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_sinfx_u10rvvm2(values));
+  }
+  Vectorized<float> sinh() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_sinhfx_u10rvvm2(values));
+  }
+  Vectorized<float> cos() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_cosfx_u10rvvm2(values));
+  }
+  Vectorized<float> cosh() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_coshfx_u10rvvm2(values));
+  }
+  Vectorized<float> ceil() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_ceilfx_rvvm2(values));
+  }
+  Vectorized<float> floor() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_floorfx_rvvm2(values));
+  }
+  Vectorized<float> neg() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(__riscv_vfneg_v_f32m2(values, VFLOAT32_VL));
+  }
+  Vectorized<float> round() const {
+    return map(at::native::round_impl);
+  }
+  Vectorized<float> tan() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_tanfx_u10rvvm2(values));
+  }
+  Vectorized<float> tanh() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_tanhfx_u10rvvm2(values));
+  }
+  Vectorized<float> trunc() const {
+    return map(at::native::trunc_impl);
+  }
+  Vectorized<float> lgamma() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_lgammafx_u10rvvm2(values));
+  }
+  Vectorized<float> sqrt() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    return Vectorized<float>(__riscv_vfsqrt_v_f32m2(values, VFLOAT32_VL));
+  }
+  Vectorized<float> reciprocal() const {
+    vfloat32m2_t values = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vfdiv_vv_f32m2(
+        __riscv_vfmv_v_f_f32m2(1.0f, VFLOAT32_VL), values, VFLOAT32_VL);
+    return Vectorized<float>(res);
+  }
+  Vectorized<float> rsqrt() const {
+    return this->sqrt().reciprocal();
+  }
+  Vectorized<float> pow(const Vectorized<float>& exp) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(exp.values, VFLOAT32_VL);
+    return Vectorized<float>(Sleef_powfx_u10rvvm2(a, b));
+  }
+
+  Vectorized<float> operator==(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmfeq_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(merge_res);
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> operator!=(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmfeq_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(
+        __riscv_vnot_v_u32m2(merge_res, VFLOAT32_VL));
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> operator<(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmflt_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(merge_res);
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> operator<=(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmfle_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(merge_res);
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> operator>(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmfgt_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(merge_res);
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> operator>=(const Vectorized<float>& other) const {
+    vfloat32m2_t a = __riscv_vle32_v_f32m2(this->values, VFLOAT32_VL);
+    vfloat32m2_t b = __riscv_vle32_v_f32m2(other.values, VFLOAT32_VL);
+    vbool16_t cmp_res = __riscv_vmfge_vv_f32m2_b16(a, b, VFLOAT32_VL);
+    vuint32m2_t merge_res = __riscv_vmerge_vvm_u32m2(
+        __riscv_vmv_v_x_u32m2(0x0, VFLOAT32_VL),
+        __riscv_vmv_v_x_u32m2(UINT32_MAX, VFLOAT32_VL),
+        cmp_res,
+        VFLOAT32_VL);
+    vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(merge_res);
+    return Vectorized<float>(res);
+  }
+
+  Vectorized<float> eq(const Vectorized<float>& other) const;
+  Vectorized<float> ne(const Vectorized<float>& other) const;
+  Vectorized<float> gt(const Vectorized<float>& other) const;
+  Vectorized<float> ge(const Vectorized<float>& other) const;
+  Vectorized<float> lt(const Vectorized<float>& other) const;
+  Vectorized<float> le(const Vectorized<float>& other) const;
+};
+
+template <>
+Vectorized<float> inline operator+(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  return __riscv_vfadd_vv_f32m2(a, b, VFLOAT32_VL);
+}
+
+template <>
+Vectorized<float> inline operator-(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  return __riscv_vfsub_vv_f32m2(a, b, VFLOAT32_VL);
+}
+
+template <>
+Vectorized<float> inline operator*(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  return __riscv_vfmul_vv_f32m2(a, b, VFLOAT32_VL);
+}
+
+template <>
+Vectorized<float> inline operator/(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  return __riscv_vfdiv_vv_f32m2(a, b, VFLOAT32_VL);
+}
+
+inline Vectorized<float> Vectorized<float>::frac() const {
+  return *this - this->trunc();
+}
+
+template <>
+Vectorized<float> inline maximum(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  vbool16_t mask = __riscv_vmand_mm_b16(
+      __riscv_vmfeq_vv_f32m2_b16(a, a, VFLOAT32_VL),
+      __riscv_vmfeq_vv_f32m2_b16(b, b, VFLOAT32_VL),
+      VFLOAT32_VL);
+  vfloat32m2_t max_res = __riscv_vfmax_vv_f32m2(a, b, VFLOAT32_VL);
+  vfloat32m2_t res = __riscv_vmerge_vvm_f32m2(
+      __riscv_vfmv_v_f_f32m2(NAN, VFLOAT32_VL), max_res, mask, VFLOAT32_VL);
+  return Vectorized<float>(res);
+}
+
+template <>
+Vectorized<float> inline minimum(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  vbool16_t mask = __riscv_vmand_mm_b16(
+      __riscv_vmfeq_vv_f32m2_b16(a, a, VFLOAT32_VL),
+      __riscv_vmfeq_vv_f32m2_b16(b, b, VFLOAT32_VL),
+      VFLOAT32_VL);
+  vfloat32m2_t min_res = __riscv_vfmin_vv_f32m2(a, b, VFLOAT32_VL);
+  vfloat32m2_t res = __riscv_vmerge_vvm_f32m2(
+      __riscv_vfmv_v_f_f32m2(NAN, VFLOAT32_VL), min_res, mask, VFLOAT32_VL);
+  return Vectorized<float>(res);
+}
+
+template <>
+Vectorized<float> inline clamp(
+    const Vectorized<float>& a,
+    const Vectorized<float>& min,
+    const Vectorized<float>& max) {
+  return minimum(max, maximum(min, a));
+}
+
+template <>
+Vectorized<float> inline clamp_max(
+    const Vectorized<float>& a,
+    const Vectorized<float>& max) {
+  return minimum(max, a);
+}
+
+template <>
+Vectorized<float> inline clamp_min(
+    const Vectorized<float>& a,
+    const Vectorized<float>& min) {
+  return maximum(min, a);
+}
+
+template <>
+Vectorized<float> inline operator&(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vand_vv_u32m2(
+      __riscv_vreinterpret_v_f32m2_u32m2(a),
+      __riscv_vreinterpret_v_f32m2_u32m2(b),
+      VFLOAT32_VL));
+  return Vectorized<float>(res);
+}
+
+template <>
+Vectorized<float> inline operator|(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vor_vv_u32m2(
+      __riscv_vreinterpret_v_f32m2_u32m2(a),
+      __riscv_vreinterpret_v_f32m2_u32m2(b),
+      VFLOAT32_VL));
+  return Vectorized<float>(res);
+}
+
+template <>
+Vectorized<float> inline operator^(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b) {
+  vfloat32m2_t res = __riscv_vreinterpret_v_u32m2_f32m2(__riscv_vxor_vv_u32m2(
+      __riscv_vreinterpret_v_f32m2_u32m2(a),
+      __riscv_vreinterpret_v_f32m2_u32m2(b),
+      VFLOAT32_VL));
+  return Vectorized<float>(res);
+}
+
+inline Vectorized<float> Vectorized<float>::eq(
+    const Vectorized<float>& other) const {
+  return (*this == other) & Vectorized<float>(1.0f);
+}
+
+inline Vectorized<float> Vectorized<float>::ne(
+    const Vectorized<float>& other) const {
+  return (*this != other) & Vectorized<float>(1.0f);
+}
+
+inline Vectorized<float> Vectorized<float>::gt(
+    const Vectorized<float>& other) const {
+  return (*this > other) & Vectorized<float>(1.0f);
+}
+
+inline Vectorized<float> Vectorized<float>::ge(
+    const Vectorized<float>& other) const {
+  return (*this >= other) & Vectorized<float>(1.0f);
+}
+
+inline Vectorized<float> Vectorized<float>::lt(
+    const Vectorized<float>& other) const {
+  return (*this < other) & Vectorized<float>(1.0f);
+}
+
+inline Vectorized<float> Vectorized<float>::le(
+    const Vectorized<float>& other) const {
+  return (*this <= other) & Vectorized<float>(1.0f);
+}
+
+template <>
+inline void convert(const float* src, int32_t* dst, int64_t n) {
+  int64_t i;
+#ifndef __msvc_cl__
+#pragma unroll
+#endif
+  for (i = 0; i <= (n - Vectorized<float>::size());
+       i += Vectorized<float>::size()) {
+    __riscv_vse32_v_i32m2(
+        dst + i,
+        __riscv_vfcvt_rtz_x_f_v_i32m2(
+            __riscv_vle32_v_f32m2(src + i, VFLOAT32_VL), VFLOAT32_VL),
+        VFLOAT32_VL);
+  }
+#ifndef __msvc_cl__
+#pragma unroll
+#endif
+  for (; i < n; i++) {
+    dst[i] = static_cast<int32_t>(src[i]);
+  }
+}
+
+template <>
+inline void convert(const int32_t* src, float* dst, int64_t n) {
+  int64_t i;
+#ifndef __msvc_cl__
+#pragma unroll
+#endif
+  for (i = 0; i <= (n - Vectorized<float>::size());
+       i += Vectorized<float>::size()) {
+    __riscv_vse32_v_f32m2(
+        dst + i,
+        __riscv_vfcvt_f_x_v_f32m2(
+            __riscv_vle32_v_i32m2(src + i, VFLOAT32_VL), VFLOAT32_VL),
+        VFLOAT32_VL);
+  }
+#ifndef __msvc_cl__
+#pragma unroll
+#endif
+  for (; i < n; i++) {
+    dst[i] = static_cast<float>(src[i]);
+  }
+}
+
+template <>
+Vectorized<float> inline fmadd(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b,
+    const Vectorized<float>& c) {
+  return __riscv_vfmacc_vv_f32m2(c, a, b, VFLOAT32_VL);
+}
+
+template <>
+Vectorized<float> inline fmsub(
+    const Vectorized<float>& a,
+    const Vectorized<float>& b,
+    const Vectorized<float>& c) {
+  return __riscv_vfmsac_vv_f32m2(c, a, b, VFLOAT32_VL);
+}
+
+} // namespace CPU_CAPABILITY
+} // namespace at::vec
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_qint32.h b/aten/src/ATen/cpu/vec/rvv/vec_qint32.h
new file mode 100644
index 0000000000000..4db48db67827d
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_qint32.h
@@ -0,0 +1,167 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/rvv/rvv_helper.h>
+#include <ATen/cpu/vec/vec_base.h>
+#include <ATen/native/quantized/AffineQuantizerBase.h>
+#include <c10/util/qint32.h>
+#include <array>
+
+namespace at {
+namespace vec {
+inline namespace CPU_CAPABILITY {
+
+template <>
+struct Vectorized<c10::qint32> {
+ private:
+  fixed_vint32m2_t vals;
+
+ public:
+  static constexpr int size() {
+    return VQINT32_VL;
+  }
+
+  static constexpr int float_num_vecs() {
+    return size() / Vectorized<float>::size();
+  }
+  static constexpr int int_num_vecs() {
+    return size() / Vectorized<int32_t>::size();
+  }
+
+  using float_vec_return_type = std::array<Vectorized<float>, 1>;
+  using int_vec_return_type = std::array<Vectorized<c10::qint32>, 1>;
+  using value_type = typename c10::qint32::underlying;
+
+  Vectorized() {}
+  Vectorized(vint32m2_t v) {
+    __riscv_vse32_v_i32m2(vals, v, VQINT32_VL);
+  }
+  // Broadcast constructor
+  Vectorized(const c10::qint32& val) {
+    vint32m2_t v = __riscv_vmv_v_x_i32m2(val.val_, VQINT32_VL);
+    __riscv_vse32_v_i32m2(vals, v, VQINT32_VL);
+  }
+
+  operator vint32m2_t() const {
+    return __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+  }
+
+  void store(void* ptr, int count = size()) const {
+    std::memcpy(ptr, this->vals, count * sizeof(value_type));
+  }
+
+  static Vectorized<c10::qint32> loadu(const void* ptr, int count = size()) {
+    __at_align__ value_type tmp_values[size()];
+    for (const auto i : c10::irange(size())) {
+      tmp_values[i] = 0;
+    }
+    std::memcpy(
+        tmp_values,
+        reinterpret_cast<const value_type*>(ptr),
+        count * sizeof(value_type));
+    return __riscv_vle32_v_i32m2(tmp_values, VQINT32_VL);
+  }
+
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> /*zero_point*/,
+      Vectorized<float> scale_zp_premul) const {
+    vint32m2_t vals = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vfloat32m2_t float_vals = __riscv_vfcvt_f_x_v_f32m2(vals, VQINT32_VL);
+    return {vec::fmadd(scale, Vectorized<float>(float_vals), scale_zp_premul)};
+  }
+
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> zero_point) const {
+    vint32m2_t vals = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vfloat32m2_t float_vals = __riscv_vfcvt_f_x_v_f32m2(vals, VQINT32_VL);
+    return {(Vectorized<float>(float_vals) - zero_point) * scale};
+  }
+
+  static Vectorized<c10::qint32> quantize(
+      const float_vec_return_type& rhs,
+      float scale,
+      int32_t zero_point,
+      float inverse_scale) {
+    Vectorized<c10::qint32> retval;
+    auto rhs_data = (vfloat32m2_t)rhs[0];
+    at::native::quantize_vec<c10::qint32, /*precision=*/32>(
+        scale, zero_point, (float*)&rhs_data, (c10::qint32*)&retval.vals, 8);
+    return retval;
+  }
+
+  Vectorized<c10::qint32> maximum(Vectorized<c10::qint32> b) const {
+    vint32m2_t x = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vint32m2_t y = __riscv_vle32_v_i32m2(b.vals, VQINT32_VL);
+    return __riscv_vmax_vv_i32m2(x, y, VQINT32_VL);
+  }
+
+  Vectorized<c10::qint32> minimum(Vectorized<c10::qint32> b) const {
+    vint32m2_t x = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vint32m2_t y = __riscv_vle32_v_i32m2(b.vals, VQINT32_VL);
+    return __riscv_vmin_vv_i32m2(x, y, VQINT32_VL);
+  }
+
+  Vectorized<c10::qint32> relu(Vectorized<c10::qint32> zero_point) const {
+    return maximum(zero_point);
+  }
+
+  Vectorized<c10::qint32> relu6(
+      Vectorized<c10::qint32> zero_point,
+      Vectorized<c10::qint32> q_six) {
+    vint32m2_t vals = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vint32m2_t zero_point_vals =
+        __riscv_vle32_v_i32m2(zero_point.vals, VQINT32_VL);
+    vint32m2_t q_six_vals = __riscv_vle32_v_i32m2(q_six.vals, VQINT32_VL);
+    return __riscv_vmin_vv_i32m2(
+        __riscv_vmax_vv_i32m2(vals, zero_point_vals, VQINT32_VL),
+        q_six_vals,
+        VQINT32_VL);
+  }
+
+  int_vec_return_type widening_subtract(Vectorized<c10::qint32> b) const {
+    vint32m2_t x = __riscv_vle32_v_i32m2(this->vals, VQINT32_VL);
+    vint32m2_t y = __riscv_vle32_v_i32m2(b.vals, VQINT32_VL);
+    return {__riscv_vsub_vv_i32m2(x, y, VQINT32_VL)};
+  }
+
+  static Vectorized<c10::qint32> requantize_from_int(
+      const int_vec_return_type& inp,
+      float multiplier,
+      int32_t zero_point) {
+    vfloat32m2_t multiplier_v = __riscv_vfmv_v_f_f32m2(multiplier, VQINT32_VL);
+    vint32m2_t zero_point_v = __riscv_vmv_v_x_i32m2(zero_point, VQINT32_VL);
+    vfloat32m2_t scaled = __riscv_vfmul_vv_f32m2(
+        __riscv_vfcvt_f_x_v_f32m2(inp[0], VQINT32_VL),
+        multiplier_v,
+        VQINT32_VL);
+    vint32m2_t rounded = __riscv_vfcvt_x_f_v_i32m2(scaled, VQINT32_VL);
+    return __riscv_vadd_vv_i32m2(rounded, zero_point_v, VQINT32_VL);
+  }
+};
+
+template <>
+Vectorized<c10::qint32> inline maximum(
+    const Vectorized<c10::qint32>& a,
+    const Vectorized<c10::qint32>& b) {
+  return a.maximum(b);
+}
+
+template <>
+Vectorized<c10::qint32> inline operator*(
+    const Vectorized<c10::qint32>& a,
+    const Vectorized<c10::qint32>& b) {
+  return __riscv_vmul_vv_i32m2(a, b, VQINT32_VL);
+}
+
+template <>
+Vectorized<c10::qint32> inline operator+(
+    const Vectorized<c10::qint32>& a,
+    const Vectorized<c10::qint32>& b) {
+  return __riscv_vadd_vv_i32m2(a, b, VQINT32_VL);
+}
+
+} // namespace CPU_CAPABILITY
+} // namespace vec
+} // namespace at
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_qint8.h b/aten/src/ATen/cpu/vec/rvv/vec_qint8.h
new file mode 100644
index 0000000000000..4edd8765bbde0
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_qint8.h
@@ -0,0 +1,340 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/rvv/rvv_helper.h>
+#include <ATen/cpu/vec/vec_base.h>
+#include <c10/util/qint8.h>
+#include <array>
+
+namespace at {
+namespace vec {
+inline namespace CPU_CAPABILITY {
+
+template <>
+struct Vectorized<c10::qint8> {
+ private:
+  fixed_vint8m2_t vals;
+
+ public:
+  static constexpr int size() {
+    return VQINT8_VL;
+  }
+
+  static constexpr int float_num_vecs() {
+    return size() / Vectorized<float>::size();
+  }
+  static constexpr int int_num_vecs() {
+    return size() / Vectorized<int32_t>::size();
+  }
+
+  using float_vec_return_type = std::array<Vectorized<float>, 4>;
+  using int_vec_return_type = std::array<Vectorized<c10::qint32>, 4>;
+  using value_type = typename c10::qint8::underlying;
+
+  Vectorized() {}
+  Vectorized(vint8m2_t v) {
+    __riscv_vse8_v_i8m2(vals, v, VQINT8_VL);
+  }
+  // Broadcast constructor
+  Vectorized(const c10::qint8& val) {
+    vint8m2_t v = __riscv_vmv_v_x_i8m2(val.val_, VQINT8_VL);
+    __riscv_vse8_v_i8m2(vals, v, VQINT8_VL);
+  }
+
+  Vectorized(const Vectorized<c10::qint8>& other) {
+    std::memcpy(vals, other.vals, sizeof(vals));
+  }
+
+  operator vint8m2_t() const {
+    return __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+  }
+
+  void store(void* ptr, int count = size()) const {
+    std::memcpy(ptr, this->vals, count);
+  }
+
+  static Vectorized<c10::qint8> loadu(const void* ptr, int count = size()) {
+    vint8m2_t zero_vec = __riscv_vmv_v_x_i8m2(0, VQINT8_VL);
+    return __riscv_vle8_v_i8m2_tu(
+        zero_vec, reinterpret_cast<const value_type*>(ptr), count);
+  }
+
+ public:
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> zero_point,
+      Vectorized<float> scale_zp_premul) const {
+    vint8m2_t vals = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint64m2_t i64_vec = __riscv_vreinterpret_v_i8m2_i64m2(vals);
+
+    vint64m2_t int_val0 = __riscv_vslidedown_vx_i64m2(i64_vec, 0, 4);
+    vint64m2_t int_val1 = __riscv_vslidedown_vx_i64m2(i64_vec, 1, 4);
+    vint64m2_t int_val2 = __riscv_vslidedown_vx_i64m2(i64_vec, 2, 4);
+    vint64m2_t int_val3 = __riscv_vslidedown_vx_i64m2(i64_vec, 3, 4);
+
+    vint8m2_t i8_val0 = __riscv_vreinterpret_v_i64m2_i8m2(int_val0);
+    vint8m2_t i8_val1 = __riscv_vreinterpret_v_i64m2_i8m2(int_val1);
+    vint8m2_t i8_val2 = __riscv_vreinterpret_v_i64m2_i8m2(int_val2);
+    vint8m2_t i8_val3 = __riscv_vreinterpret_v_i64m2_i8m2(int_val3);
+
+    vfloat32m2_t float_val0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val0), 8),
+        8);
+    vfloat32m2_t float_val1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val1), 8),
+        8);
+    vfloat32m2_t float_val2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val2), 8),
+        8);
+    vfloat32m2_t float_val3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val3), 8),
+        8);
+
+    auto val0 =
+        vec::fmadd(scale, Vectorized<float>(float_val0), scale_zp_premul);
+    auto val1 =
+        vec::fmadd(scale, Vectorized<float>(float_val1), scale_zp_premul);
+    auto val2 =
+        vec::fmadd(scale, Vectorized<float>(float_val2), scale_zp_premul);
+    auto val3 =
+        vec::fmadd(scale, Vectorized<float>(float_val3), scale_zp_premul);
+    return {val0, val1, val2, val3};
+  }
+
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> zero_point) const {
+    vint8m2_t vals = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint64m2_t i64_vec = __riscv_vreinterpret_v_i8m2_i64m2(vals);
+
+    vint64m2_t int_val0 = __riscv_vslidedown_vx_i64m2(i64_vec, 0, 4);
+    vint64m2_t int_val1 = __riscv_vslidedown_vx_i64m2(i64_vec, 1, 4);
+    vint64m2_t int_val2 = __riscv_vslidedown_vx_i64m2(i64_vec, 2, 4);
+    vint64m2_t int_val3 = __riscv_vslidedown_vx_i64m2(i64_vec, 3, 4);
+
+    vint8m2_t i8_val0 = __riscv_vreinterpret_v_i64m2_i8m2(int_val0);
+    vint8m2_t i8_val1 = __riscv_vreinterpret_v_i64m2_i8m2(int_val1);
+    vint8m2_t i8_val2 = __riscv_vreinterpret_v_i64m2_i8m2(int_val2);
+    vint8m2_t i8_val3 = __riscv_vreinterpret_v_i64m2_i8m2(int_val3);
+
+    vfloat32m2_t float_val0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val0), 8),
+        8);
+    vfloat32m2_t float_val1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val1), 8),
+        8);
+    vfloat32m2_t float_val2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val2), 8),
+        8);
+    vfloat32m2_t float_val3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val3), 8),
+        8);
+
+    auto val0 = (Vectorized<float>(float_val0) - zero_point) * scale;
+    auto val1 = (Vectorized<float>(float_val1) - zero_point) * scale;
+    auto val2 = (Vectorized<float>(float_val2) - zero_point) * scale;
+    auto val3 = (Vectorized<float>(float_val3) - zero_point) * scale;
+    return {val0, val1, val2, val3};
+  }
+
+  static Vectorized<c10::qint8> quantize(
+      const float_vec_return_type& rhs,
+      float scale,
+      int32_t zero_point,
+      float inverse_scale) {
+    Vectorized<float> vf0 = rhs[0];
+    Vectorized<float> vf1 = rhs[1];
+    Vectorized<float> vf2 = rhs[2];
+    Vectorized<float> vf3 = rhs[3];
+
+    vfloat32m2_t vecf0 = __riscv_vfmul_vf_f32m2(vf0, inverse_scale, 8);
+    vfloat32m2_t vecf1 = __riscv_vfmul_vf_f32m2(vf1, inverse_scale, 8);
+    vfloat32m2_t vecf2 = __riscv_vfmul_vf_f32m2(vf2, inverse_scale, 8);
+    vfloat32m2_t vecf3 = __riscv_vfmul_vf_f32m2(vf3, inverse_scale, 8);
+
+    vecf0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf0, __RISCV_FRM_RNE, 8), 8);
+    vecf1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf1, __RISCV_FRM_RNE, 8), 8);
+    vecf2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf2, __RISCV_FRM_RNE, 8), 8);
+    vecf3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf3, __RISCV_FRM_RNE, 8), 8);
+
+    vecf0 = __riscv_vfadd_vf_f32m2(vecf0, (float)zero_point, 8);
+    vecf1 = __riscv_vfadd_vf_f32m2(vecf1, (float)zero_point, 8);
+    vecf2 = __riscv_vfadd_vf_f32m2(vecf2, (float)zero_point, 8);
+    vecf3 = __riscv_vfadd_vf_f32m2(vecf3, (float)zero_point, 8);
+
+    vint32m2_t veci0 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf0, 8);
+    vint32m2_t veci1 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf1, 8);
+    vint32m2_t veci2 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf2, 8);
+    vint32m2_t veci3 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf3, 8);
+
+    vint16m1_t vecshi0 = __riscv_vnclip_wx_i16m1(veci0, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi1 = __riscv_vnclip_wx_i16m1(veci1, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi2 = __riscv_vnclip_wx_i16m1(veci2, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi3 = __riscv_vnclip_wx_i16m1(veci3, 0, __RISCV_VXRM_RDN, 8);
+
+    vint8m2_t vec0 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi0, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec1 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi1, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec2 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi2, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec3 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi3, 0, __RISCV_VXRM_RDN, 8));
+
+    vint8m2_t res;
+    res = __riscv_vslideup_vx_i8m2(vec0, vec1, 8, VQINT8_VL);
+    res = __riscv_vslideup_vx_i8m2(res, vec2, 16, VQINT8_VL);
+    res = __riscv_vslideup_vx_i8m2(res, vec3, 24, VQINT8_VL);
+    return Vectorized<c10::qint8>(res);
+  }
+
+  Vectorized<c10::qint8> maximum(Vectorized<c10::qint8> b) const {
+    vint8m2_t x = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint8m2_t y = __riscv_vle8_v_i8m2(b.vals, VQINT8_VL);
+    return __riscv_vmax_vv_i8m2(x, y, VQINT8_VL);
+  }
+
+  Vectorized<c10::qint8> minimum(Vectorized<c10::qint8> b) const {
+    vint8m2_t x = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint8m2_t y = __riscv_vle8_v_i8m2(b.vals, VQINT8_VL);
+    return __riscv_vmin_vv_i8m2(x, y, VQINT8_VL);
+  }
+
+  Vectorized<c10::qint8> relu(Vectorized<c10::qint8> zero_point) const {
+    return maximum(zero_point);
+  }
+
+  Vectorized<c10::qint8> relu6(
+      Vectorized<c10::qint8> zero_point,
+      Vectorized<c10::qint8> q_six) {
+    vint8m2_t vals = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint8m2_t zero_point_vals = __riscv_vle8_v_i8m2(zero_point.vals, VQINT8_VL);
+    vint8m2_t q_six_vals = __riscv_vle8_v_i8m2(q_six.vals, VQINT8_VL);
+    return __riscv_vmin_vv_i8m2(
+        __riscv_vmax_vv_i8m2(vals, zero_point_vals, VQINT8_VL),
+        q_six_vals,
+        VQINT8_VL);
+  }
+
+  int_vec_return_type widening_subtract(Vectorized<c10::qint8> b) const {
+    vint8m2_t vals = __riscv_vle8_v_i8m2(this->vals, VQINT8_VL);
+    vint64m2_t vals_i64_vec = __riscv_vreinterpret_v_i8m2_i64m2(vals);
+
+    vint64m2_t int_val0 = __riscv_vslidedown_vx_i64m2(vals_i64_vec, 0, 4);
+    vint64m2_t int_val1 = __riscv_vslidedown_vx_i64m2(vals_i64_vec, 1, 4);
+    vint64m2_t int_val2 = __riscv_vslidedown_vx_i64m2(vals_i64_vec, 2, 4);
+    vint64m2_t int_val3 = __riscv_vslidedown_vx_i64m2(vals_i64_vec, 3, 4);
+
+    vint8m2_t i8_val0 = __riscv_vreinterpret_v_i64m2_i8m2(int_val0);
+    vint8m2_t i8_val1 = __riscv_vreinterpret_v_i64m2_i8m2(int_val1);
+    vint8m2_t i8_val2 = __riscv_vreinterpret_v_i64m2_i8m2(int_val2);
+    vint8m2_t i8_val3 = __riscv_vreinterpret_v_i64m2_i8m2(int_val3);
+
+    vint32m2_t int32_val0 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val0), 8);
+    vint32m2_t int32_val1 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val1), 8);
+    vint32m2_t int32_val2 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val2), 8);
+    vint32m2_t int32_val3 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_val3), 8);
+
+    vint8m2_t b_vals = __riscv_vle8_v_i8m2(b.vals, VQINT8_VL);
+    vint64m2_t b_i64_vec = __riscv_vreinterpret_v_i8m2_i64m2(b_vals);
+
+    vint64m2_t int_b0 = __riscv_vslidedown_vx_i64m2(b_i64_vec, 0, 4);
+    vint64m2_t int_b1 = __riscv_vslidedown_vx_i64m2(b_i64_vec, 1, 4);
+    vint64m2_t int_b2 = __riscv_vslidedown_vx_i64m2(b_i64_vec, 2, 4);
+    vint64m2_t int_b3 = __riscv_vslidedown_vx_i64m2(b_i64_vec, 3, 4);
+
+    vint8m2_t i8_b0 = __riscv_vreinterpret_v_i64m2_i8m2(int_b0);
+    vint8m2_t i8_b1 = __riscv_vreinterpret_v_i64m2_i8m2(int_b1);
+    vint8m2_t i8_b2 = __riscv_vreinterpret_v_i64m2_i8m2(int_b2);
+    vint8m2_t i8_b3 = __riscv_vreinterpret_v_i64m2_i8m2(int_b3);
+
+    vint32m2_t int32_b0 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_b0), 8);
+    vint32m2_t int32_b1 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_b1), 8);
+    vint32m2_t int32_b2 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_b2), 8);
+    vint32m2_t int32_b3 =
+        __riscv_vsext_vf4_i32m2(__riscv_vlmul_trunc_v_i8m2_i8mf2(i8_b3), 8);
+
+    vint32m2_t res_0 = __riscv_vsub_vv_i32m2(int32_val0, int32_b0, 8);
+    vint32m2_t res_1 = __riscv_vsub_vv_i32m2(int32_val1, int32_b1, 8);
+    vint32m2_t res_2 = __riscv_vsub_vv_i32m2(int32_val2, int32_b2, 8);
+    vint32m2_t res_3 = __riscv_vsub_vv_i32m2(int32_val3, int32_b3, 8);
+
+    return {
+        Vectorized<c10::qint32>(res_0),
+        Vectorized<c10::qint32>(res_1),
+        Vectorized<c10::qint32>(res_2),
+        Vectorized<c10::qint32>(res_3)};
+  }
+
+  static Vectorized<c10::qint8> requantize_from_int(
+      const int_vec_return_type& inp,
+      float multiplier,
+      int32_t zero_point) {
+    Vectorized<c10::qint32> vi0 = inp[0];
+    Vectorized<c10::qint32> vi1 = inp[1];
+    Vectorized<c10::qint32> vi2 = inp[2];
+    Vectorized<c10::qint32> vi3 = inp[3];
+
+    vfloat32m2_t vecf0 = __riscv_vfcvt_f_x_v_f32m2(vi0, 8);
+    vfloat32m2_t vecf1 = __riscv_vfcvt_f_x_v_f32m2(vi1, 8);
+    vfloat32m2_t vecf2 = __riscv_vfcvt_f_x_v_f32m2(vi2, 8);
+    vfloat32m2_t vecf3 = __riscv_vfcvt_f_x_v_f32m2(vi3, 8);
+
+    vecf0 = __riscv_vfmul_vf_f32m2(vecf0, multiplier, 8);
+    vecf1 = __riscv_vfmul_vf_f32m2(vecf1, multiplier, 8);
+    vecf2 = __riscv_vfmul_vf_f32m2(vecf2, multiplier, 8);
+    vecf3 = __riscv_vfmul_vf_f32m2(vecf3, multiplier, 8);
+
+    vint32m2_t veci0 = __riscv_vfcvt_x_f_v_i32m2(vecf0, 8);
+    vint32m2_t veci1 = __riscv_vfcvt_x_f_v_i32m2(vecf1, 8);
+    vint32m2_t veci2 = __riscv_vfcvt_x_f_v_i32m2(vecf2, 8);
+    vint32m2_t veci3 = __riscv_vfcvt_x_f_v_i32m2(vecf3, 8);
+
+    veci0 = __riscv_vadd_vx_i32m2(veci0, zero_point, 8);
+    veci1 = __riscv_vadd_vx_i32m2(veci1, zero_point, 8);
+    veci2 = __riscv_vadd_vx_i32m2(veci2, zero_point, 8);
+    veci3 = __riscv_vadd_vx_i32m2(veci3, zero_point, 8);
+
+    vint16m1_t vecshi0 = __riscv_vnclip_wx_i16m1(veci0, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi1 = __riscv_vnclip_wx_i16m1(veci1, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi2 = __riscv_vnclip_wx_i16m1(veci2, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi3 = __riscv_vnclip_wx_i16m1(veci3, 0, __RISCV_VXRM_RDN, 8);
+
+    vint8m2_t vec0 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi0, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec1 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi1, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec2 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi2, 0, __RISCV_VXRM_RDN, 8));
+    vint8m2_t vec3 = __riscv_vlmul_ext_v_i8mf2_i8m2(
+        __riscv_vnclip_wx_i8mf2(vecshi3, 0, __RISCV_VXRM_RDN, 8));
+
+    vint8m2_t res;
+    res = __riscv_vslideup_vx_i8m2(vec0, vec1, 8, VQINT8_VL);
+    res = __riscv_vslideup_vx_i8m2(res, vec2, 16, VQINT8_VL);
+    res = __riscv_vslideup_vx_i8m2(res, vec3, 24, VQINT8_VL);
+    return Vectorized<c10::qint8>(res);
+  }
+};
+
+template <>
+Vectorized<c10::qint8> inline maximum(
+    const Vectorized<c10::qint8>& a,
+    const Vectorized<c10::qint8>& b) {
+  return a.maximum(b);
+}
+
+} // namespace CPU_CAPABILITY
+} // namespace vec
+} // namespace at
diff --git a/aten/src/ATen/cpu/vec/rvv/vec_quint8.h b/aten/src/ATen/cpu/vec/rvv/vec_quint8.h
new file mode 100644
index 0000000000000..a0ebce4886797
--- /dev/null
+++ b/aten/src/ATen/cpu/vec/rvv/vec_quint8.h
@@ -0,0 +1,367 @@
+#pragma once
+
+#include <ATen/cpu/vec/intrinsics.h>
+#include <ATen/cpu/vec/rvv/rvv_helper.h>
+#include <ATen/cpu/vec/vec_base.h>
+#include <c10/util/quint8.h>
+#include <array>
+
+namespace at {
+namespace vec {
+inline namespace CPU_CAPABILITY {
+
+template <>
+struct Vectorized<c10::quint8> {
+ private:
+  fixed_vuint8m2_t vals;
+
+ public:
+  static constexpr int size() {
+    return VQUINT8_VL;
+  }
+
+  static constexpr int float_num_vecs() {
+    return size() / Vectorized<float>::size();
+  }
+  static constexpr int int_num_vecs() {
+    return size() / Vectorized<int32_t>::size();
+  }
+
+  using float_vec_return_type = std::array<Vectorized<float>, 4>;
+  using int_vec_return_type = std::array<Vectorized<c10::qint32>, 4>;
+  using value_type = typename c10::quint8::underlying;
+
+  Vectorized() {}
+  Vectorized(vuint8m2_t v) {
+    __riscv_vse8_v_u8m2(vals, v, VQUINT8_VL);
+  }
+  // Broadcast constructor
+  Vectorized(const c10::quint8& val) {
+    vuint8m2_t v = __riscv_vmv_v_x_u8m2(val.val_, VQUINT8_VL);
+    __riscv_vse8_v_u8m2(vals, v, VQUINT8_VL);
+  }
+
+  Vectorized(const Vectorized<c10::quint8>& other) {
+    std::memcpy(vals, other.vals, sizeof(vals));
+  }
+
+  operator vuint8m2_t() const {
+    return __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+  }
+
+  void store(void* ptr, int count = size()) const {
+    std::memcpy(ptr, this->vals, count);
+  }
+
+  static Vectorized<c10::quint8> loadu(const void* ptr, int count = size()) {
+    vuint8m2_t zero_vec = __riscv_vmv_v_x_u8m2(0, VQUINT8_VL);
+    return __riscv_vle8_v_u8m2_tu(
+        zero_vec, reinterpret_cast<const value_type*>(ptr), count);
+  }
+
+ public:
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> zero_point,
+      Vectorized<float> scale_zp_premul) const {
+    vuint8m2_t vals = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint64m2_t u64_vec = __riscv_vreinterpret_v_u8m2_u64m2(vals);
+
+    vuint64m2_t uint_val0 = __riscv_vslidedown_vx_u64m2(u64_vec, 0, 4);
+    vuint64m2_t uint_val1 = __riscv_vslidedown_vx_u64m2(u64_vec, 1, 4);
+    vuint64m2_t uint_val2 = __riscv_vslidedown_vx_u64m2(u64_vec, 2, 4);
+    vuint64m2_t uint_val3 = __riscv_vslidedown_vx_u64m2(u64_vec, 3, 4);
+
+    vuint8m2_t u8_val0 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val0);
+    vuint8m2_t u8_val1 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val1);
+    vuint8m2_t u8_val2 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val2);
+    vuint8m2_t u8_val3 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val3);
+
+    vfloat32m2_t float_val0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val0), 8)),
+        8);
+    vfloat32m2_t float_val1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val1), 8)),
+        8);
+    vfloat32m2_t float_val2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val2), 8)),
+        8);
+    vfloat32m2_t float_val3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val3), 8)),
+        8);
+
+    auto val0 =
+        vec::fmadd(scale, Vectorized<float>(float_val0), scale_zp_premul);
+    auto val1 =
+        vec::fmadd(scale, Vectorized<float>(float_val1), scale_zp_premul);
+    auto val2 =
+        vec::fmadd(scale, Vectorized<float>(float_val2), scale_zp_premul);
+    auto val3 =
+        vec::fmadd(scale, Vectorized<float>(float_val3), scale_zp_premul);
+    return {val0, val1, val2, val3};
+  }
+
+  float_vec_return_type dequantize(
+      Vectorized<float> scale,
+      Vectorized<float> zero_point) const {
+    vuint8m2_t vals = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint64m2_t u64_vec = __riscv_vreinterpret_v_u8m2_u64m2(vals);
+
+    vuint64m2_t uint_val0 = __riscv_vslidedown_vx_u64m2(u64_vec, 0, 4);
+    vuint64m2_t uint_val1 = __riscv_vslidedown_vx_u64m2(u64_vec, 1, 4);
+    vuint64m2_t uint_val2 = __riscv_vslidedown_vx_u64m2(u64_vec, 2, 4);
+    vuint64m2_t uint_val3 = __riscv_vslidedown_vx_u64m2(u64_vec, 3, 4);
+
+    vuint8m2_t u8_val0 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val0);
+    vuint8m2_t u8_val1 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val1);
+    vuint8m2_t u8_val2 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val2);
+    vuint8m2_t u8_val3 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val3);
+
+    vfloat32m2_t float_val0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val0), 8)),
+        8);
+    vfloat32m2_t float_val1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val1), 8)),
+        8);
+    vfloat32m2_t float_val2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val2), 8)),
+        8);
+    vfloat32m2_t float_val3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vreinterpret_v_u32m2_i32m2(__riscv_vzext_vf4_u32m2(
+            __riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val3), 8)),
+        8);
+
+    auto val0 = (Vectorized<float>(float_val0) - zero_point) * scale;
+    auto val1 = (Vectorized<float>(float_val1) - zero_point) * scale;
+    auto val2 = (Vectorized<float>(float_val2) - zero_point) * scale;
+    auto val3 = (Vectorized<float>(float_val3) - zero_point) * scale;
+    return {val0, val1, val2, val3};
+  }
+
+  static Vectorized<c10::quint8> quantize(
+      const float_vec_return_type& rhs,
+      float scale,
+      int32_t zero_point,
+      float inverse_scale) {
+    Vectorized<float> vf0 = rhs[0];
+    Vectorized<float> vf1 = rhs[1];
+    Vectorized<float> vf2 = rhs[2];
+    Vectorized<float> vf3 = rhs[3];
+
+    vfloat32m2_t vecf0 = __riscv_vfmul_vf_f32m2(vf0, inverse_scale, 8);
+    vfloat32m2_t vecf1 = __riscv_vfmul_vf_f32m2(vf1, inverse_scale, 8);
+    vfloat32m2_t vecf2 = __riscv_vfmul_vf_f32m2(vf2, inverse_scale, 8);
+    vfloat32m2_t vecf3 = __riscv_vfmul_vf_f32m2(vf3, inverse_scale, 8);
+
+    vecf0 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf0, __RISCV_FRM_RNE, 8), 8);
+    vecf1 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf1, __RISCV_FRM_RNE, 8), 8);
+    vecf2 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf2, __RISCV_FRM_RNE, 8), 8);
+    vecf3 = __riscv_vfcvt_f_x_v_f32m2(
+        __riscv_vfcvt_x_f_v_i32m2_rm(vecf3, __RISCV_FRM_RNE, 8), 8);
+
+    vecf0 = __riscv_vfadd_vf_f32m2(vecf0, (float)zero_point, 8);
+    vecf1 = __riscv_vfadd_vf_f32m2(vecf1, (float)zero_point, 8);
+    vecf2 = __riscv_vfadd_vf_f32m2(vecf2, (float)zero_point, 8);
+    vecf3 = __riscv_vfadd_vf_f32m2(vecf3, (float)zero_point, 8);
+
+    vint32m2_t veci0 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf0, 8);
+    vint32m2_t veci1 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf1, 8);
+    vint32m2_t veci2 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf2, 8);
+    vint32m2_t veci3 = __riscv_vfcvt_rtz_x_f_v_i32m2(vecf3, 8);
+
+    vuint16m1_t vecshi0 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vnclip_wx_i16m1(veci0, 0, __RISCV_VXRM_RDN, 8));
+    vuint16m1_t vecshi1 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vnclip_wx_i16m1(veci1, 0, __RISCV_VXRM_RDN, 8));
+    vuint16m1_t vecshi2 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vnclip_wx_i16m1(veci2, 0, __RISCV_VXRM_RDN, 8));
+    vuint16m1_t vecshi3 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vnclip_wx_i16m1(veci3, 0, __RISCV_VXRM_RDN, 8));
+
+    vuint8m2_t vec0 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecshi0, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec1 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecshi1, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec2 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecshi2, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec3 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecshi3, 0, __RISCV_VXRM_RDN, 8));
+
+    vuint8m2_t res;
+    res = __riscv_vslideup_vx_u8m2(vec0, vec1, 8, VQUINT8_VL);
+    res = __riscv_vslideup_vx_u8m2(res, vec2, 16, VQUINT8_VL);
+    res = __riscv_vslideup_vx_u8m2(res, vec3, 24, VQUINT8_VL);
+    return Vectorized<c10::quint8>(res);
+  }
+
+  Vectorized<c10::quint8> maximum(Vectorized<c10::quint8> b) const {
+    vuint8m2_t x = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint8m2_t y = __riscv_vle8_v_u8m2(b.vals, VQUINT8_VL);
+    return __riscv_vmaxu_vv_u8m2(x, y, VQUINT8_VL);
+  }
+
+  Vectorized<c10::quint8> minimum(Vectorized<c10::quint8> b) const {
+    vuint8m2_t x = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint8m2_t y = __riscv_vle8_v_u8m2(b.vals, VQUINT8_VL);
+    return __riscv_vminu_vv_u8m2(x, y, VQUINT8_VL);
+  }
+
+  Vectorized<c10::quint8> relu(Vectorized<c10::quint8> zero_point) const {
+    return maximum(zero_point);
+  }
+
+  Vectorized<c10::quint8> relu6(
+      Vectorized<c10::quint8> zero_point,
+      Vectorized<c10::quint8> q_six) {
+    vuint8m2_t vals = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint8m2_t zero_point_vals =
+        __riscv_vle8_v_u8m2(zero_point.vals, VQUINT8_VL);
+    vuint8m2_t q_six_vals = __riscv_vle8_v_u8m2(q_six.vals, VQUINT8_VL);
+    return __riscv_vminu_vv_u8m2(
+        __riscv_vmaxu_vv_u8m2(vals, zero_point_vals, VQUINT8_VL),
+        q_six_vals,
+        VQUINT8_VL);
+  }
+
+  int_vec_return_type widening_subtract(Vectorized<c10::quint8> b) const {
+    vuint8m2_t vals = __riscv_vle8_v_u8m2(this->vals, VQUINT8_VL);
+    vuint64m2_t vals_u64_vec = __riscv_vreinterpret_v_u8m2_u64m2(vals);
+
+    vuint64m2_t uint_val0 = __riscv_vslidedown_vx_u64m2(vals_u64_vec, 0, 4);
+    vuint64m2_t uint_val1 = __riscv_vslidedown_vx_u64m2(vals_u64_vec, 1, 4);
+    vuint64m2_t uint_val2 = __riscv_vslidedown_vx_u64m2(vals_u64_vec, 2, 4);
+    vuint64m2_t uint_val3 = __riscv_vslidedown_vx_u64m2(vals_u64_vec, 3, 4);
+
+    vuint8m2_t u8_val0 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val0);
+    vuint8m2_t u8_val1 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val1);
+    vuint8m2_t u8_val2 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val2);
+    vuint8m2_t u8_val3 = __riscv_vreinterpret_v_u64m2_u8m2(uint_val3);
+
+    vint32m2_t int32_val0 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val0), 8));
+    vint32m2_t int32_val1 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val1), 8));
+    vint32m2_t int32_val2 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val2), 8));
+    vint32m2_t int32_val3 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_val3), 8));
+
+    vuint8m2_t b_vals = __riscv_vle8_v_u8m2(b.vals, VQUINT8_VL);
+    vuint64m2_t b_u64_vec = __riscv_vreinterpret_v_u8m2_u64m2(b_vals);
+
+    vuint64m2_t uint_b0 = __riscv_vslidedown_vx_u64m2(b_u64_vec, 0, 4);
+    vuint64m2_t uint_b1 = __riscv_vslidedown_vx_u64m2(b_u64_vec, 1, 4);
+    vuint64m2_t uint_b2 = __riscv_vslidedown_vx_u64m2(b_u64_vec, 2, 4);
+    vuint64m2_t uint_b3 = __riscv_vslidedown_vx_u64m2(b_u64_vec, 3, 4);
+
+    vuint8m2_t u8_b0 = __riscv_vreinterpret_v_u64m2_u8m2(uint_b0);
+    vuint8m2_t u8_b1 = __riscv_vreinterpret_v_u64m2_u8m2(uint_b1);
+    vuint8m2_t u8_b2 = __riscv_vreinterpret_v_u64m2_u8m2(uint_b2);
+    vuint8m2_t u8_b3 = __riscv_vreinterpret_v_u64m2_u8m2(uint_b3);
+
+    vint32m2_t int32_b0 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_b0), 8));
+    vint32m2_t int32_b1 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_b1), 8));
+    vint32m2_t int32_b2 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_b2), 8));
+    vint32m2_t int32_b3 = __riscv_vreinterpret_v_u32m2_i32m2(
+        __riscv_vzext_vf4_u32m2(__riscv_vlmul_trunc_v_u8m2_u8mf2(u8_b3), 8));
+
+    vint32m2_t res_0 = __riscv_vsub_vv_i32m2(int32_val0, int32_b0, 8);
+    vint32m2_t res_1 = __riscv_vsub_vv_i32m2(int32_val1, int32_b1, 8);
+    vint32m2_t res_2 = __riscv_vsub_vv_i32m2(int32_val2, int32_b2, 8);
+    vint32m2_t res_3 = __riscv_vsub_vv_i32m2(int32_val3, int32_b3, 8);
+
+    return {
+        Vectorized<c10::qint32>(res_0),
+        Vectorized<c10::qint32>(res_1),
+        Vectorized<c10::qint32>(res_2),
+        Vectorized<c10::qint32>(res_3)};
+  }
+
+  static Vectorized<c10::quint8> requantize_from_int(
+      const int_vec_return_type& inp,
+      float multiplier,
+      int32_t zero_point) {
+    Vectorized<c10::qint32> vi0 = inp[0];
+    Vectorized<c10::qint32> vi1 = inp[1];
+    Vectorized<c10::qint32> vi2 = inp[2];
+    Vectorized<c10::qint32> vi3 = inp[3];
+
+    vfloat32m2_t vecf0 = __riscv_vfcvt_f_x_v_f32m2(vi0, 8);
+    vfloat32m2_t vecf1 = __riscv_vfcvt_f_x_v_f32m2(vi1, 8);
+    vfloat32m2_t vecf2 = __riscv_vfcvt_f_x_v_f32m2(vi2, 8);
+    vfloat32m2_t vecf3 = __riscv_vfcvt_f_x_v_f32m2(vi3, 8);
+
+    vecf0 = __riscv_vfmul_vf_f32m2(vecf0, multiplier, 8);
+    vecf1 = __riscv_vfmul_vf_f32m2(vecf1, multiplier, 8);
+    vecf2 = __riscv_vfmul_vf_f32m2(vecf2, multiplier, 8);
+    vecf3 = __riscv_vfmul_vf_f32m2(vecf3, multiplier, 8);
+
+    vint32m2_t veci0 = __riscv_vfcvt_x_f_v_i32m2(vecf0, 8);
+    vint32m2_t veci1 = __riscv_vfcvt_x_f_v_i32m2(vecf1, 8);
+    vint32m2_t veci2 = __riscv_vfcvt_x_f_v_i32m2(vecf2, 8);
+    vint32m2_t veci3 = __riscv_vfcvt_x_f_v_i32m2(vecf3, 8);
+
+    veci0 = __riscv_vadd_vx_i32m2(veci0, zero_point, 8);
+    veci1 = __riscv_vadd_vx_i32m2(veci1, zero_point, 8);
+    veci2 = __riscv_vadd_vx_i32m2(veci2, zero_point, 8);
+    veci3 = __riscv_vadd_vx_i32m2(veci3, zero_point, 8);
+
+    vint16m1_t vecshi0 = __riscv_vnclip_wx_i16m1(veci0, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi1 = __riscv_vnclip_wx_i16m1(veci1, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi2 = __riscv_vnclip_wx_i16m1(veci2, 0, __RISCV_VXRM_RDN, 8);
+    vint16m1_t vecshi3 = __riscv_vnclip_wx_i16m1(veci3, 0, __RISCV_VXRM_RDN, 8);
+
+    vbool16_t neg_mask0 = __riscv_vmslt_vx_i16m1_b16(vecshi0, 0, 8);
+    vbool16_t neg_mask1 = __riscv_vmslt_vx_i16m1_b16(vecshi1, 0, 8);
+    vbool16_t neg_mask2 = __riscv_vmslt_vx_i16m1_b16(vecshi2, 0, 8);
+    vbool16_t neg_mask3 = __riscv_vmslt_vx_i16m1_b16(vecshi3, 0, 8);
+
+    vuint16m1_t vecu0 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vmerge_vxm_i16m1(vecshi0, 0, neg_mask0, 8));
+    vuint16m1_t vecu1 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vmerge_vxm_i16m1(vecshi1, 0, neg_mask1, 8));
+    vuint16m1_t vecu2 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vmerge_vxm_i16m1(vecshi2, 0, neg_mask2, 8));
+    vuint16m1_t vecu3 = __riscv_vreinterpret_v_i16m1_u16m1(
+        __riscv_vmerge_vxm_i16m1(vecshi3, 0, neg_mask3, 8));
+
+    vuint8m2_t vec0 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecu0, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec1 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecu1, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec2 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecu2, 0, __RISCV_VXRM_RDN, 8));
+    vuint8m2_t vec3 = __riscv_vlmul_ext_v_u8mf2_u8m2(
+        __riscv_vnclipu_wx_u8mf2(vecu3, 0, __RISCV_VXRM_RDN, 8));
+
+    vuint8m2_t res;
+    res = __riscv_vslideup_vx_u8m2(vec0, vec1, 8, VQUINT8_VL);
+    res = __riscv_vslideup_vx_u8m2(res, vec2, 16, VQUINT8_VL);
+    res = __riscv_vslideup_vx_u8m2(res, vec3, 24, VQUINT8_VL);
+    return Vectorized<c10::quint8>(res);
+  }
+};
+
+template <>
+Vectorized<c10::quint8> inline maximum(
+    const Vectorized<c10::quint8>& a,
+    const Vectorized<c10::quint8>& b) {
+  return a.maximum(b);
+}
+
+} // namespace CPU_CAPABILITY
+} // namespace vec
+} // namespace at
diff --git a/aten/src/ATen/cpu/vec/vec256/vec256.h b/aten/src/ATen/cpu/vec/vec256/vec256.h
index 80d42b3da6882..3a03e54f0abbd 100644
--- a/aten/src/ATen/cpu/vec/vec256/vec256.h
+++ b/aten/src/ATen/cpu/vec/vec256/vec256.h
@@ -8,7 +8,7 @@
 #include <ATen/cpu/vec/vec_base.h>
 #if !(                                                 \
     defined(__VSX__) || defined(CPU_CAPABILITY_VSX) || \
-    defined(CPU_CAPABILITY_ZVECTOR))
+    defined(CPU_CAPABILITY_ZVECTOR) || defined(CPU_CAPABILITY_RVV))
 #if defined(CPU_CAPABILITY_SVE256)
 #include <ATen/cpu/vec/sve/vec_common_sve.h>
 #else
@@ -27,6 +27,8 @@
 // clang-format on
 #elif defined(__VSX__) || defined(CPU_CAPABILITY_VSX)
 #include <ATen/cpu/vec/vec256/vsx/vec256_common_vsx.h>
+#elif defined(CPU_CAPABILITY_RVV)
+#include <ATen/cpu/vec/rvv/vec_common_rvv.h>
 #else
 // clang-format off
 #include <ATen/cpu/vec/vec256/zarch/vec256_zarch.h>
diff --git a/aten/src/ATen/cpu/vec/vec_base.h b/aten/src/ATen/cpu/vec/vec_base.h
index 562b89014717a..561902a95beb3 100644
--- a/aten/src/ATen/cpu/vec/vec_base.h
+++ b/aten/src/ATen/cpu/vec/vec_base.h
@@ -80,6 +80,17 @@ Windows llvm will not have this definition.
 #define __at_align__
 #endif
 #define VECTOR_WIDTH 16
+#elif defined(CPU_CAPABILITY_RVV)
+// Assume that RISC-V is using only GCC/Clang
+// TODO: vector size supposedly parameterized by __riscv_v_min_vlen * LMUL
+// However, RVV code still hardwired for 256-bit vector (VLEN==128 * LMUL==2)
+// right now. Placing configuration macros here, further enablement for later.
+#define CONFIG_VLEN_BITS __riscv_v_min_vlen
+#define CONFIG_LMUL 2
+#define CONFIG_VLMAX_BITS (CONFIG_VLEN_BITS * CONFIG_LMUL)
+#define CONFIG_VLMAX (CONFIG_VLMAX_BITS / 8)
+#define __at_align__ __attribute__((aligned(CONFIG_VLMAX)))
+#define VECTOR_WIDTH (CONFIG_VLMAX)
 #else // CPU_CAPABILITY_AVX512
 #if defined(__GNUC__)
 #define __at_align__ __attribute__((aligned(32)))
diff --git a/aten/src/ATen/native/DispatchStub.cpp b/aten/src/ATen/native/DispatchStub.cpp
index 515d8baeec502..738f9868921eb 100644
--- a/aten/src/ATen/native/DispatchStub.cpp
+++ b/aten/src/ATen/native/DispatchStub.cpp
@@ -62,6 +62,10 @@ static CPUCapability compute_cpu_capability() {
         return CPUCapability::DEFAULT;
       }
     }
+#elif defined(HAVE_RVV_CPU_DEFINITION)
+    if (envar == "rvv") {
+      return CPUCapability::RVV;
+    }
 #else
 #ifdef HAVE_AVX512_CPU_DEFINITION
     if (envar == "avx512") {
@@ -96,6 +100,11 @@ static CPUCapability compute_cpu_capability() {
     if (cpuinfo_has_x86_avx2() && cpuinfo_has_x86_fma3()) {
       return CPUCapability::AVX2;
     }
+#endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+    if (cpuinfo_has_riscv_v()) {
+      return CPUCapability::RVV;
+    }
 #endif
   }
 #endif
@@ -147,6 +156,9 @@ DispatchResult DispatchStubImpl::try_get_call_ptr(
   , void *SVE128
   , void *SVE256
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  , void *RVV
+#endif
 ) {
   constexpr auto supported_devices = std::to_array<c10::DeviceType>(
         {c10::DeviceType::CPU,
@@ -182,6 +194,9 @@ DispatchResult DispatchStubImpl::try_get_call_ptr(
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
           , ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+          , RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
           , SVE128
           , SVE256
@@ -243,6 +258,9 @@ void* DispatchStubImpl::get_call_ptr(
   , void *SVE128
   , void *SVE256
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  , void *RVV
+#endif
 ) {
 
   auto result = try_get_call_ptr(
@@ -264,6 +282,10 @@ void* DispatchStubImpl::get_call_ptr(
       ,
       ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+      ,
+      RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
       ,
       SVE128
@@ -300,6 +322,9 @@ DispatchResult DispatchStubImpl::try_choose_cpu_impl(
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
     , void *ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+    , void *RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
     , void *SVE128
     , void *SVE256
@@ -331,6 +356,11 @@ DispatchResult DispatchStubImpl::try_choose_cpu_impl(
     return VSX != nullptr ? DispatchResult(VSX) : ErrorType::MissingDeviceKernel;
   }
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  if (capability >= static_cast<int>(CPUCapability::RVV)) {
+    return RVV != nullptr ? DispatchResult(RVV) : ErrorType::MissingDeviceKernel;
+  }
+#endif
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
   if (capability >= static_cast<int>(CPUCapability::ZVECTOR)) {
     return ZVECTOR != nullptr ? DispatchResult(ZVECTOR) : ErrorType::MissingDeviceKernel;
@@ -371,6 +401,9 @@ void* DispatchStubImpl::choose_cpu_impl(
   , void *SVE128
   , void *SVE256
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  , void *RVV
+#endif
 ) {
   auto capability = static_cast<int>(get_cpu_capability());
   (void)capability;
@@ -406,6 +439,12 @@ void* DispatchStubImpl::choose_cpu_impl(
     return ZVECTOR;
   }
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  if (capability >= static_cast<int>(CPUCapability::RVV)) {
+    TORCH_INTERNAL_ASSERT(RVV, "DispatchStub: missing RVV kernel");
+    return RVV;
+  }
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
   if (capability == static_cast<int>(CPUCapability::SVE128)) {
     if (C10_UNLIKELY(!SVE128)) {
diff --git a/aten/src/ATen/native/DispatchStub.h b/aten/src/ATen/native/DispatchStub.h
index 73fbd1da1b9e0..d2cc21c890c45 100644
--- a/aten/src/ATen/native/DispatchStub.h
+++ b/aten/src/ATen/native/DispatchStub.h
@@ -67,6 +67,8 @@ enum class CPUCapability {
 #elif defined(HAVE_SVE_CPU_DEFINITION)
   SVE256 = 1,
   SVE128 = 2,
+#elif defined(HAVE_RVV_CPU_DEFINITION)
+  RVV = 1,
 #else
   AVX2 = 1,
   AVX512 = 2,
@@ -116,6 +118,9 @@ struct TORCH_API DispatchStubImpl {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
       , void *ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+      , void *RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
       , void *SVE128
       , void *SVE256
@@ -138,6 +143,9 @@ struct TORCH_API DispatchStubImpl {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
     , void *ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+    , void *RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
     , void *SVE128
     , void *SVE256
@@ -160,6 +168,9 @@ struct TORCH_API DispatchStubImpl {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
       , void *ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+      , void *RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
       , void *SVE128
       , void *SVE256
@@ -185,6 +196,9 @@ struct TORCH_API DispatchStubImpl {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
     , void *ZVECTOR
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+    , void *RVV
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
     , void *SVE128
     , void *SVE256
@@ -243,6 +257,9 @@ struct DispatchStub<rT (*)(Args...), T> {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
       , reinterpret_cast<void*>(ZVECTOR)
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+      , reinterpret_cast<void*>(RVV)
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
       , reinterpret_cast<void*>(SVE128)
       , reinterpret_cast<void*>(SVE256)
@@ -305,6 +322,9 @@ struct DispatchStub<rT (*)(Args...), T> {
 #ifdef HAVE_ZVECTOR_CPU_DEFINITION
       , reinterpret_cast<void*>(ZVECTOR)
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+      , reinterpret_cast<void*>(RVV)
+#endif
 #ifdef HAVE_SVE_CPU_DEFINITION
       , reinterpret_cast<void*>(SVE128)
       , reinterpret_cast<void*>(SVE256)
@@ -333,6 +353,9 @@ struct DispatchStub<rT (*)(Args...), T> {
   static TORCH_API FnPtr SVE128;
   static TORCH_API FnPtr SVE256;
 #endif
+#ifdef HAVE_RVV_CPU_DEFINITION
+  static TORCH_API FnPtr RVV;
+#endif
 private:
   DispatchStubImpl impl;
 };
@@ -442,6 +465,12 @@ struct RegisterPRIVATEUSE1Dispatch {
 #define REGISTER_SVE256_DISPATCH(name, fn)
 #endif
 
+#ifdef HAVE_RVV_CPU_DEFINITION
+#define REGISTER_RVV_DISPATCH(name, fn) REGISTER_ARCH_DISPATCH(name, RVV, fn)
+#else
+#define REGISTER_RVV_DISPATCH(name, fn)
+#endif
+
 // Macro to register the same kernel for all CPU arch types. This is useful
 // if a kernel does not benefit from being recompiled across different arch types.
 #define REGISTER_ALL_CPU_DISPATCH(name, fn)                                    \
@@ -451,7 +480,8 @@ struct RegisterPRIVATEUSE1Dispatch {
   REGISTER_VSX_DISPATCH(name, fn)                                              \
   REGISTER_ZVECTOR_DISPATCH(name, fn)                                          \
   REGISTER_SVE128_DISPATCH(name, fn)                                           \
-  REGISTER_SVE256_DISPATCH(name, fn)
+  REGISTER_SVE256_DISPATCH(name, fn)                                           \
+  REGISTER_RVV_DISPATCH(name, fn)
 
 #define REGISTER_NO_CPU_DISPATCH(name)                                         \
   REGISTER_ALL_CPU_DISPATCH(name, nullptr)
diff --git a/aten/src/ATen/native/cpu/LerpKernel.cpp b/aten/src/ATen/native/cpu/LerpKernel.cpp
index 6881eddfd674b..a22e2344b097d 100644
--- a/aten/src/ATen/native/cpu/LerpKernel.cpp
+++ b/aten/src/ATen/native/cpu/LerpKernel.cpp
@@ -19,7 +19,7 @@ Vectorized<scalar_t> is_lerp_weight_small(Vectorized<scalar_t> weight) {
 // is_lerp_weight_small doesn't work for complex because z.abs() returns a
 // complex vector which can't be compared. Either implement it with z.abs_2_(),
 // or fallback to the scalar function.
-#if !(defined(CPU_CAPABILITY_DEFAULT) || defined(_MSC_VER) || defined(CPU_CAPABILITY_SVE256) || defined(CPU_CAPABILITY_SVE128))
+#if !(defined(CPU_CAPABILITY_DEFAULT) || defined(_MSC_VER) || defined(CPU_CAPABILITY_SVE256) || defined(CPU_CAPABILITY_SVE128) || defined(CPU_CAPABILITY_RVV))
 template <typename value_t>
 Vectorized<c10::complex<value_t>> is_lerp_weight_small(Vectorized<c10::complex<value_t>> weight) {
   using vec_reg_t = decltype(weight.abs_2_());
diff --git a/aten/src/ATen/test/vec_test_all_types.cpp b/aten/src/ATen/test/vec_test_all_types.cpp
index 4d132a93c0fdc..62d4be739de40 100644
--- a/aten/src/ATen/test/vec_test_all_types.cpp
+++ b/aten/src/ATen/test/vec_test_all_types.cpp
@@ -2392,7 +2392,7 @@ namespace {
       }
     }
 #endif
-#if !defined(CPU_CAPABILITY_SVE256)
+#if !(defined(CPU_CAPABILITY_SVE256) || defined(CPU_CAPABILITY_RVV))
     TYPED_TEST(VecMaskTests, Cast) {
       using vec = TypeParam;
       using src_t = ValueType<TypeParam>;
diff --git a/aten/src/ATen/test/vec_test_all_types.h b/aten/src/ATen/test/vec_test_all_types.h
index 14368db92707f..55f766cc13cbc 100644
--- a/aten/src/ATen/test/vec_test_all_types.h
+++ b/aten/src/ATen/test/vec_test_all_types.h
@@ -53,7 +53,7 @@ CACHE_ALIGN #define
   }
 
 #if defined(CPU_CAPABILITY_ZVECTOR) || defined(CPU_CAPABILITY_VSX) || defined(CPU_CAPABILITY_AVX2) || \
-  defined(CPU_CAPABILITY_AVX512) && (defined(__GNUC__) || defined(__GNUG__))
+  defined(CPU_CAPABILITY_AVX512) || defined(CPU_CAPABILITY_RVV)  && (defined(__GNUC__) || defined(__GNUG__))
 #undef CHECK_DEQUANT_WITH_LOW_PRECISION
 #define CHECK_WITH_FMA 1
 #elif defined(CPU_CAPABILITY_SVE256)
diff --git a/cmake/Codegen.cmake b/cmake/Codegen.cmake
index ca7ed49de6a8f..70033fbe60ffb 100644
--- a/cmake/Codegen.cmake
+++ b/cmake/Codegen.cmake
@@ -442,6 +442,12 @@ if(INTERN_BUILD_ATEN_OPS)
     list(APPEND CPU_CAPABILITY_FLAGS "${OPT_FLAG} -march=armv8-a+sve+bf16 -D__ARM_FEATURE_BF16 -msve-vector-bits=128")
   endif()
 
+  if(CXX_RVV_FOUND)
+    SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DHAVE_RVV_CPU_DEFINITION")
+    LIST(APPEND CPU_CAPABILITY_NAMES "RVV")
+    LIST(APPEND CPU_CAPABILITY_FLAGS "${OPT_FLAG}  ${CXX_RVV_FLAGS}")
+  endif(CXX_RVV_FOUND)
+
   list(LENGTH CPU_CAPABILITY_NAMES NUM_CPU_CAPABILITY_NAMES)
   math(EXPR NUM_CPU_CAPABILITY_NAMES "${NUM_CPU_CAPABILITY_NAMES}-1")
 
diff --git a/cmake/Dependencies.cmake b/cmake/Dependencies.cmake
index a2dd4dacc4328..5b28b42728a43 100644
--- a/cmake/Dependencies.cmake
+++ b/cmake/Dependencies.cmake
@@ -1653,6 +1653,8 @@ if(NOT INTERN_BUILD_MOBILE)
   add_definitions(-DMINIZ_DISABLE_ZIP_READER_CRC32_CHECKS)
 
   find_package(ZVECTOR) # s390x simd support
+
+  find_package(RVV) # RISC-V simd support
 endif()
 
 #
diff --git a/cmake/Modules/FindRVV.cmake b/cmake/Modules/FindRVV.cmake
new file mode 100644
index 0000000000000..7029ed0016533
--- /dev/null
+++ b/cmake/Modules/FindRVV.cmake
@@ -0,0 +1,61 @@
+IF(CMAKE_SYSTEM_NAME MATCHES "Linux")
+  message("-- <FindRVV>")
+  SET(RVV_CODE "
+    #include <riscv_vector.h>
+    int main(){
+        const float src[] = { 0.0f, 0.0f, 0.0f, 0.0f };
+        uint64_t ptr[2] = {0x0908060504020100, 0xFFFFFFFF0E0D0C0A};
+        vuint8m1_t a = __riscv_vreinterpret_v_u64m1_u8m1(__riscv_vle64_v_u64m1(ptr, 2));
+        vfloat32m1_t val = __riscv_vle32_v_f32m1((const float*)(src), 4);
+        int b = (int)__riscv_vfmv_f_s_f32m1_f32(val);
+        return 0;
+    }
+   ")
+  SET(READ_VECTOR_LENGTH_CODE "
+    #include <riscv_vector.h>
+    #include <iostream>
+    int main(){
+        unsigned long vlen_bytes = __riscv_vlenb();
+        unsigned long vlen_bits = vlen_bytes * 8;
+        std::cout << vlen_bits << std::endl;
+        return 0;
+    }
+   ")
+  file(WRITE ${CMAKE_BINARY_DIR}/read_vector_length.cpp "${READ_VECTOR_LENGTH_CODE}")
+
+  SET(ARCH_SIMD_TEST_FLAGS "-march=rv64gcv_zvl128b")
+  SET(CMAKE_REQUIRED_FLAGS_SAVE ${CMAKE_REQUIRED_FLAGS})
+  SET(CMAKE_REQUIRED_FLAGS "${ARCH_SIMD_TEST_FLAGS}")
+  CHECK_CXX_SOURCE_COMPILES("${RVV_CODE}"  COMPILE_OUT_RVV)
+  SET(CMAKE_REQUIRED_FLAGS ${CMAKE_REQUIRED_FLAGS_SAVE})
+  separate_arguments(CFLAGS_LIST UNIX_COMMAND "$ENV{CFLAGS}")
+  if(COMPILE_OUT_RVV)
+    execute_process(
+      COMMAND
+      "${CMAKE_CXX_COMPILER}"
+      ${CFLAGS_LIST}
+      "${ARCH_SIMD_TEST_FLAGS}"
+      "${CMAKE_BINARY_DIR}/read_vector_length.cpp"
+      "-o"
+      "${CMAKE_BINARY_DIR}/read_vector_length"
+      RESULT_VARIABLE VECTOR_LENGTH_CHECK_COMPILE_RESULT)
+    if(VECTOR_LENGTH_CHECK_COMPILE_RESULT)
+      message(FATAL_ERROR "Could not compile RISC-V Vector Length Check: ${VECTOR_LENGTH_CHECK_COMPILE_RESULT}")
+    endif()
+    execute_process(
+      COMMAND "${CMAKE_BINARY_DIR}/read_vector_length"
+      RESULT_VARIABLE VECTOR_LENGTH_CHECK_RESULT
+      OUTPUT_VARIABLE VLEN_BITS
+      OUTPUT_STRIP_TRAILING_WHITESPACE)
+    if(VECTOR_LENGTH_CHECK_RESULT)
+      message(WARNING "Could not run RISC-V Vector Length Check: ${VECTOR_LENGTH_CHECK_RESULT}")
+    endif()
+    message("-- RVV flags were set.")
+    message("-- RISC-V CPU Vector Length: ${VLEN_BITS} bits")
+    set(CXX_RVV_FOUND TRUE)
+    SET(CXX_RVV_FLAGS  "${ARCH_SIMD_TEST_FLAGS}" )
+  else()
+    message("-- RVV flags were NOT set.")
+  endif()
+  message("-- </FindRVV>")
+endif()
diff --git a/torch/backends/cpu/__init__.py b/torch/backends/cpu/__init__.py
index 82dc52cd4904c..8b2937b9345bd 100644
--- a/torch/backends/cpu/__init__.py
+++ b/torch/backends/cpu/__init__.py
@@ -13,6 +13,7 @@ def get_cpu_capability() -> str:
     - "DEFAULT"
     - "VSX"
     - "Z VECTOR"
+    - "RVV"
     - "NO AVX"
     - "AVX2"
     - "AVX512"
diff --git a/torch/headeronly/cpu/vec/intrinsics.h b/torch/headeronly/cpu/vec/intrinsics.h
index 3cf427dae64bc..7f2bb680d586b 100644
--- a/torch/headeronly/cpu/vec/intrinsics.h
+++ b/torch/headeronly/cpu/vec/intrinsics.h
@@ -35,6 +35,8 @@
 #elif defined(__s390x__)
 // targets Z/architecture
 // we will include vecintrin later
+#elif defined(__GNUC__) && defined(__riscv_v_intrinsic)
+#include <riscv_vector.h>
 #elif (defined(__GNUC__) || defined(__xlC__)) && \
     (defined(__VEC__) || defined(__ALTIVEC__))
 /* XLC or GCC-compatible compiler, targeting PowerPC with VMX/VSX */