[CPU: Cortex-M] Missing compiler fences in the interrupt code?

[g-berthiaume]

Looking at the Cortex-M implementation of the disable_interrupts and enable_interrupts functions, I'm surprised there are no compiler fences to ensure the compiler does not reorder the code.

I'm new to Zig, so I might be misunderstanding the Zig memory model.

What I see:

    pub fn enable_interrupts() void {
        asm volatile ("cpsie i");
    }

    pub fn disable_interrupts() void {
        asm volatile ("cpsid i");
    }

What I was expecting to see (from CMISIS_6)

__STATIC_FORCEINLINE void __enable_irq(void) {
    __asm volatile ("cpsie i" : : : "memory");
}

__STATIC_FORCEINLINE void __disable_irq(void) {
    __asm volatile ("cpsid i" : : : "memory");
}

Best !

[Grazfather]

Yes! we can fix that, but feel free to push your own PR. Good find.

[piotrfila]

AFAIK asm volatile cannot be reordered woth anything, in the standard library syscalls are implemented the same way.

[piotrfila]

My bad, std uses asm volatile (..., .{ .memory = true }), I agree we should match that

[g-berthiaume]

@Grazfather Great job. This kind of thing can be a nightmare to debug. ^^

[Grazfather]

Credit goes to you!