gen-verilog TB long tails: typed let-locals get no reg declaration; unsized concat operands; 'Syntax error defining function' class

[gHashTag]

Icarus sweep of the tri-net corpus (77 non-KAT specs): 29 pass clean, 31 fail to compile, 17 fail at runtime. Compile-error classes:

1. Typed let locals in test blocks get no reg declaration — Unable to bind wire/reg 'valid'/'score': the TB declares regs for StmtAssign bindings (fix(gen-verilog-sim): test-block reg declarations + 64-bit __mul_noop #1899) but not for typed StmtLocal bindings (the newer executable tests use let x: T = ...). Biggest class.
2. Unsized concat operands — Concatenation operand ... has indefinite width (lite_crypto): the documented {1'b1, 1} class.
3. 'Syntax error defining function' (crc16, byte_utils): some fn shape emits invalid function definitions.
4. Runtime [TEST] FAILED ×17: semantic divergences between the Verilog lowering and the (Zig/C-green) specs -- to be diagnosed one by one after the compile classes clear.

Full lists in tri-net's gft-verilog-kat.yml comment updated by the companion PR.