Surfaced during a silent-success audit of src/cli/*.zig (the audit that produced #427, where fpga-flash flash and verify-pid exited 0 on failure). Those two were unambiguous and are fixed. Three more are design-ambiguous — they belong to test/diagnostic commands, so whether a detected failure should be a non-zero exit is a policy call, not a clear bug. Flagging for a decision rather than changing behavior unilaterally.
Instances (each reports failure but returns/exits 0)
| File |
Function |
Failure it prints without exiting non-zero |
src/cli/fpga_flash.zig |
runUartTest() |
⚠️ RX empty - no echo from FPGA |
src/cli/uart_test.zig |
runPingTest() |
Success rate: 0/N (all ❌ Timeout) |
src/cli/uart_test.zig |
runLoopbackTest() |
Result: 0/12 bytes matched (❌) |
The decision
- If these are pass/fail tests (CI/scripts gate on them): a total/partial failure should exit non-zero (e.g.
error.UartTestFailed when success < count, or a threshold). This matches the now-consistent fpga-flash flash/verify-pid behavior.
- If they are interactive diagnostics (human reads the μs stats and success rate): exit 0 is fine and the current output is the deliverable.
Clean rungs of the audit — fpga_dslogic.zig (❌ lines are troubleshooting hints; real errors exit(1)) and sacred_synth.zig (return error.SynthesisFailed) — need no change.
Once you pick a policy I can apply it consistently across the three.
Surfaced during a silent-success audit of
src/cli/*.zig(the audit that produced #427, wherefpga-flash flashandverify-pidexited 0 on failure). Those two were unambiguous and are fixed. Three more are design-ambiguous — they belong to test/diagnostic commands, so whether a detected failure should be a non-zero exit is a policy call, not a clear bug. Flagging for a decision rather than changing behavior unilaterally.Instances (each reports failure but returns/exits 0)
src/cli/fpga_flash.zigrunUartTest()⚠️ RX empty - no echo from FPGAsrc/cli/uart_test.zigrunPingTest()Success rate: 0/N(all❌ Timeout)src/cli/uart_test.zigrunLoopbackTest()Result: 0/12 bytes matched(❌)The decision
error.UartTestFailedwhensuccess < count, or a threshold). This matches the now-consistentfpga-flash flash/verify-pidbehavior.Clean rungs of the audit —
fpga_dslogic.zig(❌ lines are troubleshooting hints; real errorsexit(1)) andsacred_synth.zig(return error.SynthesisFailed) — need no change.Once you pick a policy I can apply it consistently across the three.