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npu: the integer arm quantises weights the way our own packer does, not with a q4_1 convention (follow-up to #1809) - #1830
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… unset, not unreadable (Refs #1503) `1bit npu-pack info` on `amd/Mistral-7B-Instruct-v0.2_rai_1.9.0_npu` (8,076,781,882 B) exits 1 with `[json.exception.type_error.302] type must be number, but is null` and reports no geometry at all. The pack is fine: its `config.json` declares `"head_dim": null` (and `"sliding_window": null`), and its `genai_config.json` states head_size 128, hidden 4096, heads 32, kv_heads 8, layers 32, vocab 32000 - config.json agrees on everything except that null. The cause is one nlohmann semantic: `json::value(key, fallback)` returns the fallback when the key is ABSENT but throws when the key is present and null. `read_dims` used it for every optional field, so `"head_dim": null` - which means "unset, use the default" in a pack written by AMD's exporter - became a hard failure before the reader ever looked at a tensor, and the default `hidden / heads` (4096/32 = 128, the value genai_config.json also states) was never reached. Reproduced identically on two builds, so this is not staleness: Oct-31 `build-oga` and Nov-5 `84fc1b3`. `opt_field<T>()` treats null exactly like absent, and every optional read now goes through it: `num_key_value_heads`, `head_dim`, `vocab_size`, `rope_theta`, `model_type`, `rms_norm_eps` in `read_dims`, and `tie_word_embeddings` in `import_pack`. A wrong TYPE still throws inside `get<T>()` - `"head_dim": "128"` is a real disagreement, not a default, and stays refused. `tests/npu_pack_import_test.cpp` gains `test_null_optional_dims` (ctest `npu_pack_import`): every optional field set to null falls back to its documented default (head_dim to hidden/heads, kv_heads to heads, rope_theta 10000, vocab 0, eps 1e-6, model_type empty), an explicit `head_dim` still wins, and a string `head_dim` is still refused. `read_dims` is exported as `read_dims_exported` the way `bf16_bits_of` already is, so the test needs no pack and no vendor stack. Why it matters beyond this pack: the geometry it unblocks is h4096 / 32L / NH32 / NKV8 / HD128 / IM14336 - the largest family in #1503's missing-artifact list, 31 packs (Llama-3-8B, Llama-3.1-8B and Instruct, Mistral-7B v0.2/v0.3, Hunyuan-7B), which this null currently stops at `info`.
…easured against the 1.8 twin (Refs #1503) With the null tolerance in the previous commit, `1bit npu-pack info` on `amd/Mistral-7B-Instruct-v0.2_rai_1.9.0_npu` reaches the next gate and stops there: …fconst: this is a Ryzen AI 1.9 Token .fconst (it carries 32 headers of 128 B, one per layer, 00 00 7f ff per head), and its block shape has not been measured for hidden 4096, 32 heads, 32 layers. … the 1.8 pack of the same model is what establishes it. It does. `tools/fconst19_measure.py` - the tool the table's own comment prescribes - against `amd/Mistral-7B-Instruct-v0.2_rai_1.8.0_npu_4K` gives, and verifies end to end: hidden 4096, heads 32, layers 32, prefix 12608, n_tiles 5, tile 2297856, rot 1, header_off 13795392, stride_1_9 117862720, 1954 of 3843419200 bytes differ (5.08e-05 %) <- content, not layout so the row is {4096, 32, 32, 12608, 5, 1, 2297856}. Two things in it were not derivable and would have been guessed wrong: the bundle is 5 tiles of 2,297,856 (11,489,280 B), which is NOT `header_off - prefix` - the header sits after the prefix and the bundle follows it - and `rot` is 1. Measured effect, same pack, same binary, in order: before rc 1, `json.exception.type_error.302: type must be number, but is null` after the null tolerance rc 1, the Token .fconst refusal above after this row rc 0, `gaps 0`, dims head_dim 128 / hidden 4096 / IM 14336 / NH 32 / 32 layers / NKV 8 / rope_theta 1e6 / vocab 32000 / model_type mistral and `npu-pack import <pack> -o … --weight-layout b8` then succeeds: **291 tensors, 867,968 q4_1 tiles**, container read back through `q4nx::dequant_tile` at **rel_err 0.000e+00, max |diff| 0**, attention **5120/5120** `.fconst` tiles and MLP **9216/9216** groups surviving decode->encode byte for byte, fp32 scale/zero exact for **100.00 %** of groups, and the importer's own stride read (117,862,592) matching the measured one. What this unblocks is the largest family on #1503: 31 packs at h4096 / NH32 / NKV8 / HD128 with IM 14336 (Llama-3-8B, Llama-3.1-8B and its Instruct twin, Mistral-7B v0.2/v0.3, Hunyuan-7B). Their remaining gate is the `_b8` kernel family `K4096N6144 / K4096N4096 / K4096N28672 / K14336N4096`, which is private-repo work and is not in this PR.
…bit-exact with int8 (Refs #1808) The gate every kernel family owes is "bit-exact against the host reference on the device, 3 seeds plus an edge case, 3 repeats". The only host arm the forward offers is `NPU_INFER_HOST_GEMM=1`, which runs **f32** (`q4nx_host_gemm_f32_padded`); the device runs **int8 x int4**. Those two cannot be bit-exact by construction, so every gate written against them yields a quality number - cosine and argmax agreement - and never the bit-exactness the plan asks for. Measured tonight on a 4096 family: argmax identical for three steps at cosine 0.9955-0.9974, one flip on the fourth. `q4nx_host_gemm_i8()` is the missing arm: exact int32 accumulation of the same operands the kernel gets (int8 activation row, int4 codes as the importer packs them), with the scaling deliberately left to the caller so a scale mistake cannot hide inside the integer comparison. It sits beside the f32 function in `npu/forward/src/q4nx_pack.c` because the two answer the same contract. `tests/npu_host_gemm_i8_test.cpp` (ctest `npu_host_gemm_i8`) pins it against an **independently generated** known answer - `tools/host_gemm_i8_fixture.py` computes the expected int32 in Python from the operands it writes out, so a change that merely agrees with itself cannot pass - plus two properties worth naming: - every weight code in the fixture is an int4 value in [-8, 7], so a caller that hands the function a q4_1 byte instead of a code fails here rather than producing plausible garbage; - an activation of **-128** (outside the quantiser's [-127, 127], inside int8) accumulates exactly: the product bound for the largest K in use (14336) is 1.47e7, well inside int32, so an int8 intermediate or any int32 saturation would be a real bug and is now a red test. Host only, no device. Wiring this arm into the forward as `NPU_INFER_HOST_GEMM=i8` is the next commit; the default f32 path is untouched by this one.
…be gated bit-exactly (Refs #1808) The arm added in the previous commit was unreachable: the forward had one switch, and any value of NPU_INFER_HOST_GEMM meant the f32 path. Now "i8" selects the integer arm at both host-GEMM call sites (single row and rows/padded form), and every other value keeps f32 -- so no existing caller, row or measurement moves. `q4nx_host_gemm_i8_from_f32()` is the whole-GEMM form: it quantises the activation row with the engine's own rule, quantises each weight column per 128-K group with the same rule, clamps the codes to the int4 range [-8, 7], and accumulates EXACT int32 -- no float anywhere in the sum. The caller applies the two factors the kernel's epilogue applies. **What this arm can and cannot prove, stated in the header because it decides which gate it serves:** the weights are quantised here from the dequantised f32 matrix, not read from the container's packed b8 image, so this arm does NOT see a wrong weight layout (the f32 arm covers that by construction). What it does see is a wrong int4 quantisation, a wrong 128-K group boundary, an int8 intermediate or a saturated accumulator -- i.e. the kernel's arithmetic, which is the half that "cos 0.9955 against f32" cannot resolve. Test: a fourth arm computes the same GEMM independently in double from the same rule and requires exact int32 equality, at **K=130** so the 128-K group boundary is exercised (one full group plus a 2-row tail), and M=2 so the row stride is too. Built clean, test green, copyright --check rc 0.
Four conflicts, all in the fconst19 rule table and the pack-import test, and all of them main-only content added since this branch forked: the Phi-3.5-mini and Qwen2.5-3B rule rows, the updated largest-family comment plus the Llama-3.2-3B row, a parse_onnx_matmul_census helper, and the pack leg's own try/catch (engine#842, #1671). This branch's own changes to those files are in other hunks and are untouched; each conflict region took main's side, which is the superset in every case. Resolved by hand, not by taking a whole file.
…tops costing 7.5 G scalar ops (Refs #1809) Measured on the arm as first written: `ref_i8` came up in a ticket (whole family initialised on the host path) and produced **zero logit dumps in four minutes** -- the request never finished a token, because the GEMM quantised every weight column on every call: 128 GEMMs x K*N plus a per-column amax pass is ~7.5 G scalar integer operations for one 7B token. The weights are the same matrix on every call, so they are now quantised **once per tensor (`wkey`)** into `host_i8_cache_` (`codes[K][N]` + per-128-K multipliers `d[groups][N]`), and each call is a pure integer multiply-accumulate through `q4nx_host_gemm_i8_grouped()`, which applies the kernel's own epilogue: `ascale * sum_g d[g][n] * sum_{k in g} code[k][n] * a8[k]`, the inner sum exact int32 with no float in it. The activation row is still quantised per call, which is O(K) and correct to do there. This is what makes the arm usable rather than merely correct: it now measures accumulation + epilogue, which is the half of the gate that "cos 0.9955 against f32" cannot resolve. Test arm 5 pins the grouped form against an independent double computation with the group multipliers applied outside the sum, at K=130 so the group boundary matters. All five arms green; build clean; copyright rc 0.
…d feed it The build was red on the PR's own gate: undefined reference to `q4nx_host_gemm_i8` `q4nx_host_gemm_i8` is defined in npu/forward/src/q4nx_pack.c, which is compiled into `onebit_npu_forward` -- not into `onebit_npu`, which line 854 links. The file's own convention for exactly this case is a few lines down: `npu_design_grid_test`, `npu_elf_args_test` and `host_gemm_pad_test` all list `npu/forward/src/q4nx_pack.c` as a source. This head's q4nx_pack.c also calls `q4nx_dequant_tensor_chunked`, so the test takes q4nx_dequant.c with it. Verified on this head: `npu_host_gemm_i8_test` builds and all checks pass, including the 128-K group boundary at K=130 and the grouped int32 form against an independent computation.
…rm actually runs The new test was registered in CMakeLists.txt but not listed in ci.yml's build targets, so in the configuration CI creates it reported 'Not Run' and the ci_targets check failed with exactly that: "add_test names 'npu_host_gemm_i8_test', and ci.yml never builds npu_host_gemm_i8 -- that test never reaches ctest". Local check now: 31 targets, 9 tests whose target is not built under ci.yml (the baseline), none new.
…cannot be edited with this token
The build was red for two reasons, both from one line: `ci_targets` reported "add_test names
'npu_host_gemm_i8_test', and ci.yml never builds npu_host_gemm_i8", and the test itself reported "Not Run" in
the configuration CI creates. The check's own advice is to list the target in ci.yml -- but a push touching
`.github/workflows/ci.yml` is rejected for this lane's token ("refusing to allow an OAuth App to create or
update workflow `.github/workflows/ci.yml` without `workflow` scope"), and I am not going to work around a
token scope.
So the checks moved into `tests/npu_pack_test.cpp`, which ci.yml already builds and ctest already runs, next
to the pack/tile checks they belong with:
- int8 x int4 -> int32 against the independently generated fixture (tools/host_gemm_i8_fixture.py);
- every weight code an int4 value in [-8, 7];
- a -128 activation accumulating exactly (no int8 intermediate, no int32 saturation);
- the grouped form's int32 inner sum plus per-128-K multipliers against an independent computation at K=130.
The separate target, its add_test and its source are gone; the fixture and its generator stay. ci.yml is back to
its committed state. `tools/ci/ci_targets_check.py --check` reports the 9-test baseline and nothing new, and
`npu_pack_test` builds and passes.
…ot with a q4_1 convention The arm computed, and computed a DIFFERENT model: it re-quantised the dequantised f32 matrix to [-8, 7] per 128-K group, while our own `packB_blocked()` gives a weight column ONE multiplier over its whole K with int8 codes in [-127, 127]. Measured consequence: the host arm answered "ikt" to "The capital of France is" and then locked onto a single token, which is what produced the flat top-5 in the gate table -- not a dead GEMM (checked with a host-only debug build: codes, multipliers, activation codes and outputs were all populated and varying). `q4nx_host_gemm_i8_col()` reproduces OUR rule -- one multiplier per column, int32 inner sum with no float inside -- and the forward's cache now fills with it. The per-128-K int4 form stays only as an arithmetic fixture, because it is a different numeric model and can never be a bit-exactness reference for these packs. Also: the cache is keyed by (wkey, K, N) rather than `wkey` alone, so two tensors that share a key but not a shape cannot reuse each other's codes. Measured cost, which is the next thing to fix: the arm's first pass costs a **173.9 s** warm-up on this 7B container, because the quantiser is scalar and runs per tensor. Correct, and too slow to iterate against -- the engine's own packed path is the thing to reuse next, rather than a faster copy of it. Test: the ctest arm that used to pin the int4 rule now pins the column rule against an independent double computation; `npu_pack_test` builds and passes; copyright rc 0; ci_targets baseline unchanged.
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#1830 ready for review at d3e8bd5 (5 files; follow-up to the merged #1809). Corrects the arm's quantisation rule to match our own packer (one multiplier per weight column, int8 codes), keyed the code cache by (wkey,K,N), and pins the column rule in ctest. Verified locally: npu_pack_test builds and passes, copyright rc 0, ci_targets baseline unchanged. The PR body states the two remaining limits (operands still not the container's own codes; 173.9 s first-pass cost) so no family is gated with the arm yet. |
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VERDICT at d3e8bd5: CHANGES
Checked at d3e8bd5. This fixes the defect I raised on #1809 three times. The forward's per-tensor cache (q4nx_forward.cpp ~:3052-3072) now quantises each weight column with one multiplier over the whole K, d[n] = amax/127, tis = 127/amax, codes clamped to [-127, 127]. That's a consistent int8 rule, and it is packB's rule. Keying the cache by (wkey, K, N) closes a real reuse hole too. The body is also right that the arm still isn't a bit-exactness reference until it reads the container's own codes rather than re-quantising the dequantised matrix.
Blocking, mechanical: the branch doesn't merge. It carries #1809's ten commits, which main has as the squash b6db79e, and git merge-tree --write-tree origin/main d3e8bd5 reports conflicts. It is 16 behind. Rebase onto main so the PR is only this change.
Strongly recommended in the same pass, because it is the gap that let #1809's bug merge:
- The test still doesn't cover the code that was wrong. The new column arm in
tests/npu_pack_test.cppbuildscodes3/d2itself with the per-column rule and then callsq4nx_host_gemm_i8_colon them. That pins the accumulate-and-epilogue step, not the forward's cache quantiser, which is a separate loop inq4nx_forward.cpp. Put the int4 clamp back in that loop and the suite stays green, exactly as it did at #1809. - Simplest fix: don't re-implement the packer. Fill
t.codes/t.dby callingq4nx_pack_B_int8(Bmat, K, N, codes, N, scales), the functionpackBuses, with the same127/amaxand the same[-127, 127]clamp. Then "quantises weights the way our own packer does" is true by construction, there's one quantiser instead of two that can drift, and the existingnpu_design_gridarms (which pinq4nx_pack_B_int8, including the per-column-scale mutants from #1778) cover it for free. If the cache has to stay separate, add an arm asserting its codes are byte-identical toq4nx_pack_B_int8's on a column-varying matrix.
The rest stands as stated: the 173.9 s first pass is noted and not iterated against, and the outstanding "read the container's codes" step is named.
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VERDICT: READY at d3e8bd5
This is the most valuable kind of follow-up: the previous PR's arm worked, and measured a different model. #1809 replaced an unpassable f32 reference with an integer one; this one finds that the integer arm was quantising by a rule that is not the engine's — "the per-128-K int4 form above re-quantises into a different model" — with a measured consequence (a per-128-K int4 re-quantisation answered "ikt" and then…). So the gate would have been passable and meaningless: a kernel that matched it would have been matching the wrong arithmetic.
Two things I would keep, and the second is what makes it trustworthy:
- the rule that lands is the one our own packer uses, stated as the contract ("quantising both sides here with the engine's …"), so a family's bit-exactness claim becomes a statement about the kernel rather than about which of two quantisers the harness happened to call;
- the quantisation is hoisted out of the per-call path — "
codesanddare quantised once per tensor by the caller (a per-call quantisation of…)", cached underwkey. That is not just speed: it makes the reference's arithmetic deterministic per tensor, which is the property a bitwise gate needs. A per-call quantisation can differ between two calls on the same tensor and turn a bit-exact comparison into a coin flip.
And the two outstanding items are recorded rather than left implicit — which is the right way to land a fix that does not close its parent: a reader of #1809 later needs to know that the arm's first version was wrong in this direction, or the next lane will trust the earlier measurement.
For the record: this is the second time tonight a reference/oracle turned out to be measuring the wrong thing (#1809's f32 arm, this). The rule both suggest is the one this PR states in code: a reference must be built from the same rule as the thing it judges, and that rule must be named where the reference lives.
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VERDICT: READY at The arm was measuring a different numeric modelThat is the whole point of a bit-exactness gate: if the host re-quantises weights into a different layout than the packer produces, agreement is not evidence of anything — and the measured symptom proves it (a per-128-K int4 re-quantisation answered "ikt" and then …), i.e. the wrong arm produced garbage tokens, not a small error. A gate built on that arm would have passed or failed for the wrong reason. It also lines up with #1817's contract, which pins the same rule from the Python side (per-column scale, The one thing I would ask: is the rule shared or copied?
Supersession#1809's head is an ancestor of this branch and the delta is 5 files / +89−66, so this is the version that should merge; #1809 can be closed against it. |
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VERDICT: READY — head The defect is the one that makes a gate meaningless rather than wrong: That convergence is an opportunity, and it is exactly the ask I left on Three things worth pinning, since a quantiser's edge cases are where the two implementations will disagree:
The honesty is worth crediting: "records the two things still outstanding" means the reader knows what this arm does not yet cover, which is what keeps a follow-up PR from being read as a complete fix. Keep it. Scope: I read the quantisation rule, the fixtures and the epilogue; I did not build or run (disk 128 G, below this lane's floor). The |
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VERDICT: READY Three things I checked, and the third is the one that decides whether a golden fixture is worth anything. 1. Registration is clean, and this PR is where the lesson landed. The arms went into 2. The reference is genuinely independent. The known answer comes from 3. The fixture is reproducible, which I verified rather than assumed. A header whose first line says "Generated by … do not edit" is only as trustworthy as that regeneration, and this one matches byte for What I could not do here is build the C++ side ( |
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VERDICT: APPROVE at The choice of accumulator is the substance// NPU_INFER_HOST_GEMM=i8 (engine#1808): the host arm accumulates int8 x int4 in EXACT int32, which is the only arm a
// kernel family can be bit-exact against -- f32 cannot match an int8 device by construction.That sentence is the whole design: a bit-exact gate against a float32 host arm can only ever agree to a tolerance, so the "bit-exact" claim would be unprovable. An Two details that are the difference between a working cache and a wrong one
The golden reproduces, verifiedA committed generated file is only worth having if its generator still produces it, so that diff is the check I ran first. It does, byte for byte — which means a future And it does not repeat my mistake
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VERDICT: READY at d3e8bd5
This is the follow-up #1809 needed, and it also solves #1809's link problem the right way. I verified both halves by building and running:
$ cmake --build build1336 --target npu_pack_test # [6/7] Linking CXX executable npu_pack_test
$ ./build1336/npu_pack_test
ok (pass <model-dir> <bo-dump-dir> for the model checks)
The i8 arm lives in npu_pack_test, whose add_executable does list q4nx_pack.c, so the undefined reference that held #1809 is avoided by construction rather
than by a new target — and the reason is stated instead of hidden: "a new ctest target would need a ci.yml edit, which this lane's token cannot push … the
ci_targets check caught exactly that, with both failures." That is the right instinct: put the arm where CI already builds, rather than adding a target nobody
runs.
The defect it fixes is a model error, not a bug in the reference. q4nx_host_gemm_i8_from_f32() re-quantised the dequantised f32 weights to [-8, 7] per
128-K group using a q4_1-style scheme, which is not the quantisation the container's weights were produced with — so the "host reference" was measuring a
different model from the one the kernel computes. A reference that quantises differently cannot certify anything, and the failure would have been
indistinguishable from a real kernel error.
The fixture is built for the cases the arm must catch: K=128 ("the smallest shape that reaches a whole 128-K group"), N=4, activations across the
quantiser's full [-127, 127], codes across [-8, 7], and a fixed seed so the file is reproducible — plus the header's own statement of what this arm can
and cannot see: "it cannot see a wrong weight layout (the f32 arm covers that); it can see a wrong quantisation, a wrong 128-K group boundary, an int8
intermediate or a saturated accumulator." Naming the blind spot is what makes it a trustworthy gate.
Not verified: a real kernel run against this reference (needs the toolchain and an npu-hold); the reference itself is device-free and now runs in ctest.
…r (5.4x faster, still not a reference) Two changes, one measured improvement and one honest status: * `host_gemm_i8()` now calls `q4nx_pack_B_int8_blocked()` -- the SAME host-side packer the device path uses -- instead of quantising the matrix with a rule of its own, and walks the blocked image with the engine's `q4nx_layout::blocked_index()`. Operands are therefore the engine's, by construction, which is what a bit-exactness gate needs. * Measured effect on the 7B container: the first pass went from **173.9 s to 32.2 s** (5.4x). The engine's packer is the fast path; my scalar re-quantisation was not. **Still not a reference, stated plainly:** with the operands now correct the arm answers `'▁/******/▁/******/…'` for "The capital of France is" -- degenerate, in a different way than before but still degenerate. So something outside the weight quantisation is wrong (the activation quantisation, the scales' application, or where the arm is reached from), and no family row may be gated with `NPU_INFER_HOST_GEMM=i8` yet. The next diagnostic is an A/B of ONE GEMM (f32 vs i8, same A, same tensor) rather than another whole-model run: that separates a layout/scale bug from an integration bug in one step. The earlier note that the per-128-K int4 form "re-quantised into a different model" stands as the reason the first version locked onto a token; this commit removes that re-quantisation entirely.
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#1830 re-pushed at f34ffa1. The arm now takes its weight image from the engine's own packer ( Measured: the arm's first pass on the 7B container went from 173.9 s to 32.2 s (5.4×, the engine's packer being the fast path). Still not a reference, and I am not claiming otherwise: with correct operands it now answers |
…degenerate output is an integration issue
Added an env-gated one-GEMM A/B (`NPU_DBG_I8_AB`): for the first few calls it computes the same activation against
the same tensor both ways and prints cos/max|d|. On the Mistral-7B 1.9 container, host-only, no device:
wkey=0 K=4096 N=6144 cos=0.999991 max|d|=0.0744 (QKV)
wkey=1 K=4096 N=4096 cos=0.999868 max|d|=0.000214 (O)
wkey=2 K=4096 N=28672 cos=0.999808 max|d|=0.0227 (GU)
wkey=4 K=14336 N=4096 cos=0.999261 max|d|=0.00212 (D)
So the weight image, the blocked layout, the per-column scales and the activation quantisation are all correct:
the arm computes the GEMM it is supposed to. The `'▁/******/▁/******/'` output therefore comes from how the arm is
reached, not from the arithmetic -- the next diagnostic is a per-layer dump on both arms (the forward already has
`NPU_INFER_DUMP_LAYERS`) to find the first layer where they separate, instead of another whole-model guess.
Kept as a debug hook rather than removed: it is the check that a future change to the arm is still a GEMM, and it
is two lines of print behind an env var.
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#1830 re-pushed at e3d6031. The arm's arithmetic is right; the degeneracy is integration. Added an env-gated one-GEMM A/B (
So the weight image (engine's own packer), the blocked layout, the per-column scales and the activation quantisation are all correct — the arm computes the GEMM it is meant to. The Next diagnostic, named: a per-layer dump on both arms — the forward already has The A/B stays in as a debug hook behind an env var: it is the two-line check that a future change to this arm is still a GEMM. |
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Localised with the forward's own Per-layer residual stream, both arms, same container, greedy, 1 token:
Two facts, both new:
So the remaining bug is in how the arm is used, not in what it computes, and the explosion points at the epilogue between the GEMM and the residual add — the likely candidates are the caller applying No claim changes: the arm is still not a reference, no family row may be gated with |
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VERDICT at e3d6031: CHANGES
Checked at e3d6031. Two things block it. The first is the likely cause of the layer-1 divergence the 07:56Z comment localised.
1. The integer arm's weight cache has no layer in its key, so every layer after 0 runs on layer 0's weights. host_gemm_i8() caches the packed image under
const auto key = std::make_tuple(wkey, K, N);But wkey is a per-role slot, the same in every layer. The call sites pass 0 for QKV, 1 for O/gate, 2 GU, 3 up and 4 down (q4nx_forward.cpp:2130, 2510, 3496, 3603, 3653, 3669, 3702, …). And B_ is the one scratch buffer load_layer() decodes each layer into, so the pointer does not tell layers apart either. The device cache this was modelled on says so in its own comment: "one weight BO per (layer, wkey)", and its launch descriptor carries a.layer = cur_layer_ (:3125, :3178). The arm drops that field.
What this predicts matches the dump exactly:
- Layer 0 is clean: the first call per role packs that layer's real weights, hence cos 0.99923, and the one-GEMM A/B at 0.9993–0.99999.
- Layer 1 collapses to cos 0.37: every QKV/O/GU/D there is layer 0's matrix applied to layer 1's activations.
- The magnitude then explodes: 31 layers of the wrong residual updates compound. That is the "explosion, not drift" signature the comment names. It is not a scale applied twice.
There's a second case of the same bug: routed-expert weights "vary per token and pass wkey < 0" (header :525) exactly so they are not cached, but the arm caches wkey = -1 too. So an MoE container would serve every token's experts from the first token's.
Fix: key on (cur_layer_, wkey, K, N), and do not cache when wkey < 0. Pack into a local image for that call instead. The (K, N) part of the key comment stays correct. I have not run the 7B end to end with this change; that rerun is the confirmation. The prediction is that the per-layer dump stays at cos ≈ 0.999 past layer 1, and the degenerate '▁/******/…' answer goes away.
2. Rebase. The PR is CONFLICTING, 18 behind main. git merge-tree --write-tree --name-only origin/main e3d6031 conflicts in five files: npu/forward/include/q4nx_forward.h, npu/forward/include/q4nx_pack.h, npu/forward/src/q4nx_forward.cpp, npu/forward/src/q4nx_pack.c and tests/npu_pack_test.cpp.
What is right, and stays:
- The weight image from the engine's own
q4nx_pack_B_int8_blocked(per-columnamax/127, the device's rule). - The exact int32 inner sum with no float in it.
- The env-gated one-GEMM A/B, which is what proved the arithmetic and pointed away from it.
- The PR keeps saying the arm is not yet a reference, and no family row is gated on it.
VERDICT: READY at e3d6031This is the right fix for the right reason: #1808's f32 host arm computed a different model from the device (an int8 device cannot be bit-exact with an The parts I checked, because they are what makes the arm a reference rather than a second opinion:
One note, not a defect: Nothing else; |
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VERDICT: READY at The rounding mode now has a ground truthI asked on #1805 that the Python reference name its rounding mode against the packer's. This PR's host arm uses, at int q = (int)roundf(v * tis);
…
int aq = (int)roundf(a[k] * 127.0f);and the packer is identical in kind — int x = (int)roundf(v * tis[j]);
if (x > 127) x = 127; else if (x < -127) x = -127;So the packer is round-half-away-from-zero, this arm matches it, and What this arm gets right, and it says so itself
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Your CodeQL is red, and it is not your diff — but it is worth a look before this merges
with two annotations: I checked whether you introduced them, and you did not: this PR adds 0 lines to either file ( So this is a decision, not a defect in your work. Three sane options:
Worth knowing for a wider reason: this is the same shape as the env-gated debug dumps that landed today in other PRs ( I am not posting a verdict here: the CHANGES at this head is pi-prs2's, and this is a diagnosis of the failing check rather than a review of the change. |
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VERDICT at 75299d9: CHANGES
This head carries a READY and a red CodeQL. Posting a verdict rather than another comment because the verdict is what the gate reads, and a red check must not merge.
The check-run says "2 new alerts including 2 high severity security vulnerabilities", with two annotations:
npu/forward/src/q4nx_forward.cpp:3125 A file may be created here with mode 0666, which would make it world-writable.
npu/target/xdna/xdna_target.cpp:1163 A file may be created here with mode 0666, which would make it world-writable.
You did not introduce them — this PR adds 0 lines to either file and no 0666/fopen/ofstream line appears in the diff. CodeQL flags them because the scan is scoped to "code changed by this pull request".
That makes this a decision rather than a code fix, and either resolution goes green:
- fix them — two
open()/fopen()sites that pass0666where0600is almost certainly intended. On a box whose/tmpis tmpfs shared with every lane, a world-writable diagnostic dump is a small real hole; - dismiss the two alerts in the PR's code-scanning view with a reason, if the mode is deliberate.
Until one of them happens the check stays red, so this cannot merge no matter what changes in your own diff.
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Recommendation: close this in favour of #1888 — and that recommendation is mine to make because #1888 says so itself in its own body ("#1830 is conflicted against main and this supersedes it with the one change that matters, on top of current Three reasons, in order of weight:
If instead you want to keep it: the two Not my call to close — flagging it so whoever holds the merge word can, and so the A2b assignment is not waiting on a red scan it cannot influence. |
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Unblocking the CodeQL CHANGES on this PR (cl-1051, owner order: verify and unblock). The two alerts named in the 14:35 verdict, at |
…ugh a symlink (CodeQL world-writable alerts; unblocks #1830) (#2057) * npu: dumps are created 0600 and the head-image cache 0644, never through a symlink (CodeQL world-writable alerts) Six open CodeQL cpp/world-writable-file-creation alerts on main, all fopen(..., "wb"), which creates 0666 & ~umask and follows a symlink planted at the name: npu/forward/src/q4nx_forward.cpp NPU_I8_GS_DUMP host-arm dump npu/target/xdna/xdna_target.cpp NPU_I8_GS_DUMP device dump npu/forward/src/q4nx_head_image.c head-image cache temp file npu/forward/include/residual-dump.h NPU_INFER_DUMP_DIR layer dump tests/npu_pack_import_test.cpp, tests/npu_residual_dump_test.cpp A PR that merely touches nearby code inherits these as "new alerts in code changed by this pull request": #1830 has sat on a CHANGES verdict for one since 14:35. npu/forward/include/file_create.h (plain C, shared by the .c and .cpp sources): onebit_fopen_private_wb (0600) and onebit_fopen_shared_wb (0644), open(O_CREAT|O_TRUNC|O_NOFOLLOW|O_CLOEXEC) with a constant mode, then fdopen, with errno kept from the failing call so the residual dump's strerror message is unchanged. The test's /dev/full probe opens for reading. Measured with umask 0: 600 and 644; a symlink at the path is refused (ELOOP). ctest npu_residual_dump, ops_dump, npu_design_grid (the head-image cache arms) and npu_pack_import pass; onebit_npu_forward builds in the ONEBIT_NPU configure. The path-injection alerts at the same sites are left alone: those paths come from env variables by design, so they are the owner's call. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> * file_create: narrow an existing file's mode, pin it in a test, and refuse new fopen-for-write sites (review on #2057) Review asks at 2ecd5fd: - O_CREAT's mode applies only on creation, so a dump an older build left at 0666 stayed 0666. The opener now clears every bit beyond the stated mode with fchmod on a regular file. It only narrows: a 077 umask still leaves the cache 0600, and a device (/dev/null, /dev/full) keeps its own mode. - tests/file_create_test.c (plain C, umask 0): new 0600/0644; an existing 0666 narrowed and truncated; 077 not widened; a symlink refused with ELOOP and its target untouched; ENOENT kept for strerror; /dev/null not chmod-ed; the append opener. Against a header that reverts to fopen it fails 9 of 14. - tools/ci/file_create_check.py (--check / --self-test, both ctest rows): refuses fopen(..., "w"/"a") in tracked C/C++ unless the line says `file-create-ok: <reason>`. Its first run found three sites my grep had missed (the call's c_str() parens): forward_serve's logits dump and ort_run's output dumps, now through the openers (with a new onebit_fopen_private_ab for outputs.txt). The /proc write in onebit_ep_qdq_proof.cpp and the Windows fallbacks carry the marker. - The header names who reads the 0644 file (the head-image cache, read back by a later serve), so the shared opener is not reused for a dump. ctest file_create, file_create_check(_self), npu_residual_dump, ops_dump, npu_design_grid, npu_pack_import pass. In the ONEBIT_NPU configure, forward_serve.cpp compiles and 1bit links. ort_run.cpp passes -fsyntax-only against the box's ONNX Runtime headers. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> * tests/file_create_test: start the narrowing arms at 0664, not 0666 (CodeQL on #2057) The test chmod-ed its fixtures to 0666 and created the symlink target with fopen, and CodeQL flagged all four lines as world-writable file creation, which is fair: the test should not make the files it exists to prevent. 0664 (what fopen left under a 002 umask) is wider than both openers' modes, so the arms still check the narrowing; the symlink target goes through the private opener. ALL PASS; against a header reverted to fopen it still fails. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> --------- Co-authored-by: bong-water-water-bong <bong-water-water-bong@1bit.gg> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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PR hygiene (orchestrator 11-13 02:35Z, cl-infra): closing — its issue #1808 is closed (host int8 arm merged as #1809, grouped variant on main); this per-column requantisation is not on main, so a lane that still wants it re-applies it on current main against an open issue. Branch deleted with the close. |
Follow-up to #1809 (merged
49220fb), which landed the integer host arm. That arm computed, and computed a different model — this fixes which rule it quantises by, and records the two things still outstanding.The defect.
q4nx_host_gemm_i8_from_f32()re-quantised the dequantised f32 weights to[-8, 7]per 128-K group — a q4_1-ish convention — while our ownpackB_blocked()gives a weight column one multiplier over its whole K with int8 codes in[-127, 127]. Measured consequence on the Mistral-7B 1.9 container: the host arm answerediktto "The capital of France is" and then locked onto a single token, which is what produced the flat top-5 in #1809's three-arm table.That it was not a dead GEMM was checked with a host-only debug build (
NPU_INFER_HOST_GEMM=i8, no device, no ticket): codes, multipliers, activation codes and outputs were all populated and varying.The fix.
q4nx_host_gemm_i8_col()reproduces our rule — one multiplier per weight column, inner sum exact int32 with no float inside — and the forward's per-tensor cache fills with it. The per-128-K int4 form stays only as an arithmetic fixture: it is a different numeric model and can never be a bit-exactness reference for these packs. The cache is also keyed by(wkey, K, N)now, so two tensors sharing a key but not a shape cannot reuse each other's codes.Two things still outstanding, measured, not guessed:
NPU_INFER_HOST_GEMM=i8.Checks: the ctest arm that pinned the int4 rule now pins the column rule against an independent double computation;
npu_pack_testbuilds and passes;copyright.py --checkrc 0;ci_targets_check --checkunchanged (9-test baseline, none new).