[bong-water-water-bong]

Refs #799. Docs only, one file.

The plan tracker ends when its last sub-issue (P4) does. Before that happens the page's "Not yet" list should be true, and three of its entries were not:

entry	said	is
P6	"tau=0.6 and Hexagon acceptance rows are still missing"	the tau 0.6 rows are on the leaderboard (hit rate 78.77 %, depth-1 acceptance 78.34 %, docs/npu-leaderboard.md lines 37-38) and the sub-issue's final comment has both gates measured on 8 prompts x 64 tokens. Only a second target's rows are missing, because there is no second target
P5	"has no engine rows yet"	the sub-issue was finished on 2026-11-07 as a toolchain check (bit-exact in QEMU v73, a cycle model, the t2 target gate #1272). Not built: a Hexagon NpuTarget in the engine, silicon timing, the layer on the DSP
P7	listed the open work without saying the sub-issue is finished	it ended with the refusal in place (#1320) and the int8 KV writer not built

The section now opens by saying what it is: the part of the plan that was not built, so the tracker ending does not read as all seven phases shipped.

Checked against the tree at main: npu/target/ holds target.h and xdna only; --npu-target hexagon is refused by name (app/forward_serve.cpp:1097); the acceptance numbers are the leaderboard's and the P6 sub-issue's own table. No code, no measurement of mine.

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[bong-water-water-bong]

ready for review at 75f2c57

[github-actions]

PR Reviewer Guide 🔍

Here are some key observations to aid the review process:

🎫 Ticket compliance analysis 🔶 799 - Partially compliant Compliant requirements: The PR updates docs/npu-plan.md to accurately reflect what was built vs not built The tracker closes with P4, and the "Not yet" list correctly identifies what was not built The documentation correctly states that P5, P6, and P7 were not fully implemented as originally planned Non-compliant requirements: The PR does not implement the Hexagon NpuTarget in the engine The PR does not implement silicon timing for the Hexagon target The PR does not implement the decoder layer on the DSP for Hexagon The PR does not implement the cache writer/reader for int8 KV Requires further human verification: Verification that the documentation accurately reflects the current state of the codebase Confirmation that the "Not yet" list correctly identifies what was not built

⏱️ Estimated effort to review: 2 🔵🔵⚪⚪⚪

🧪 No relevant tests

🔒 No security concerns identified

⚡ Recommended focus areas for review Documentation Accuracy The documentation correctly updates the "Not yet" list to reflect what was actually built versus what was not built. However, it's important to ensure that all claims made in the documentation are verified against the actual codebase state, particularly regarding the absence of Hexagon NpuTarget implementation and silicon timing. The tracker (#799) closes with P4 (#803). What follows is the part of the plan that was **not built**, so that closing it does not read as "all seven phases shipped": each entry says what landed, what did not, and why. - **P4** (#803): **A1 landed** in #808 (`0a2cbb9`) — the `NpuTarget` interface (`npu/target/target.h`), the XDNA target behind it, and `open()` consuming the plan instead of duplicating the derivation. The step-by-step record is [npu-p4-target-split.md](npu-p4-target-split.md) §3, so this list does not snapshot it, but the two ends that touch *this* page's fields are worth naming: the plan can now **name the design set** (#1330, #1333 — `designs[]` above), and two of the three context sets are now **the target's**: the M=128 prefill ELF set in `XdnaTarget::open_prefill()` (#1380) and the lm-head context in `XdnaTarget::open_head()` (#1458, #1478) — the forward calls `open_head()` (`q4nx_forward.cpp:1357`) and then asks the target for the context (`head_ctx()`), rather than building it. **The M=16 decode family is the target's as well** (#2166, A2b: `XdnaTarget::open_decode_family()`; the forward names the designs), so all three context sets are; the optional wide and narrow sealed families are still set up by the forward. The P4 gate's two output rows are measured: window11 text identity on `bonsai2-27b-NPU` (on #803) and logits KLD 0 on eight prompts, with every logits dump byte-identical before and after the move ([npu-p4-target-split.md](npu-p4-target-split.md) §4). `XdnaTarget::load_block` remains a named no-op, so weight residency and decoding stay as they were — the cache fills lazily inside `gemv`, and turning that into an explicit block step is an optimisation whose evidence is a tokens/s row, not a structural move. - **P5** (#804, closed 2026-11-07 on the scope the owner set: a toolchain check): the t2 GEMV is bit-exact in QEMU v73 on the container's own layer-0 tensors and has a cycle model, and `tests/npu_t2_target_gate.py` (#1272) holds any t2 target to the pinned accumulation order. **Not built:** a Hexagon `NpuTarget` in the engine (`npu/target/` holds `xdna` only, and `--npu-target hexagon` is refused by name), silicon timing of our kernel (no board on the fleet), and the decoder layer composed on the DSP. - **P6** (#805, closed 2026-11-07): the shared drafter protocol is on main and measured on XDNA at both gates, 8 prompts x 64 tokens, text identical 8/8 — tau 0.6 (the default): hit rate 78.77 %, depth-1 acceptance 78.34 %, 1.83 tokens per pass; tau 0: 46.69 %, 75.14 %, 2.87 ([npu-leaderboard.md](npu-leaderboard.md), the `27b-mtp-*` rows). Leaf fill was rejected with a test (`tests/mtp_draft_test.cpp` [16]) rather than built. **Not measured:** acceptance on a second target, because there is no second target (P5). - **P7** (#806, closed 2026-11-07 with the refusal in place, the writer not built): the `kv` contract above is in the plan and its arithmetic is gated in CI (`ctest -R npu_kv_int8`, which needs no device: see below), and the **target-side refusal** is enforced as well (`npu_target_caps`, so an `int8` plan cannot be run as f16 by any target, including P5's Hexagon). Still open, in the order it can be taken: the cache **writer/reader** in the

[bong-water-water-bong]

Closing under the PR cap (16:45Z: at most two open per lane, no new PRs while main is red). This one was opened minutes before the cap and has no verdict; the branch 1bit/799-not-yet-accurate at 75f2c57 stays, and I will re-open it when my READY ones have merged.