Add decode-only disaggregated serving design-space study - #3
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Design-space exploration for the decode phase on PLENA, with prefill served by a separate unquantised BF16 chip. Enumerates 3,072 numerical profiles and 574 hardware candidates, screens them for numerical fidelity against a live model, prices survivors with an emulator-calibrated timing model, and selects a joint software and hardware configuration under an area budget. Timing rests on the stage-calibrated analytic tier, whose worst per-stage error is 4.64 percent against a 5 percent gate at 100 percent coverage. No full-model compiler-trace pricing was used at scale; that tier appears only as a bounded spot-check on the published configurations. Prefill output is bit-identical to BF16 in every configuration tested.
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Adds a new top-level decode_dse/ package; no existing files are modified.
Design-space exploration for the decode phase on PLENA, with prefill served by a separate unquantised BF16 chip. Enumerates 3,072 numerical profiles and 574 hardware candidates, screens them for numerical fidelity against a live model, prices survivors with an emulator-calibrated timing model, and selects a joint software and hardware configuration under an area budget.
Timing rests on the stage-calibrated analytic tier, whose worst per-stage error is 4.64 percent against a 5 percent gate at 100 percent coverage. No full-model compiler-trace pricing was used at scale; that tier appears only as a bounded spot-check on the published configurations.
Prefill output is bit-identical to BF16 in every configuration tested.