Circuits and Systems Lab (CASlab)

Popular repositories Loading

1. UPSET UPSET Public

   UPSET is an automated framework for performing Single Event Transient Analysis and Optimisation for VLSI circuits utilising Static Timing Analysis principles. Documentation at:

   Verilog 9 1

2. uth-pexconv uth-pexconv Public

   Parasitic extraction format converters for FasterCap and other field solvers

   Python 1