Add tapeout pad sim SV models and TapeoutSimConfig - #1
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Copy SimI2CEepromModel.sv and SimSPIFlashPadModel.sv from tape-env so existing SimPeripheral blackboxes resolve their /vsrc resources. Add TapeoutConfig and TapeoutSimConfig composing pad-level IO binders and harness models (no SMIC180, no Buckyball RoCC). Update README. Co-authored-by: Shiroha <whmio0115@gmail.com>
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Summary
Minimal slice of tape-env chip-level pad simulation, wired to the IO binders and harness models already present in this repo.
Changes
src/main/resources/vsrc/SimI2CEepromModel.sv— 256-byte I2C EEPROM behavioral model (byte[i] = i at reset)src/main/resources/vsrc/SimSPIFlashPadModel.sv— pad wrapper aroundSimSPIFlashModelsrc/main/scala/config/TapeoutConfigs.scala—TapeoutConfig,TapeoutSimConfig,WithTapeoutRocket,WithSerialConnect,WithTapeoutSingleClockREADME.md— brief description of config targetsConfig overview
TapeoutConfigTapeoutSimConfig+spiflash0=)Intentionally excluded
TapeoutBuckyballPebbleConfigNotes
SV resources match the paths already referenced by
SimPeripheralModels.scalablackboxes. Config fragments such asWithUART/WithSPI/WithI2C/WithGPIOare inherited from the upstream Chipyard dependency (same asAbstractConfig).