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1. my-cpu-results my-cpu-results Public

   Synthesis, power and verification results for a 32-bit, 5-stage pipelined DLX processor in VHDL, with eight RTL revisions and reproducible analysis.

   Tcl

2. radix4-booth-multiplier radix4-booth-multiplier Public

   Implemented three radix4 booth multipliers with wallace/dadda tree adders for partial products. Having no sign extension/ with sign extension partial products and a corrector vector, which contains…

   Verilog

3. register-level-light-controlled-fan register-level-light-controlled-fan Public

   Register-level (bare-metal) STM32L4 + FPGA light-controlled fan: ADS1115 I2C ADC, L293D PWM motor drive, W25Q32 SPI flash logging, and a VHDL UART command interface.

   C 2

4. uvm-results uvm-results Public

   SystemVerilog/UVM verification of a registered P4 adder and windowed register file, with coverage, synthesis results, report, and slides.

   TeX

5. Capacitive_Sensor_Sync Capacitive_Sensor_Sync Public

   STM32 & MATLAB project: Synchronized capacitive sensor network using XBee

   C

6. sha256-synthesis-optimization sha256-synthesis-optimization Public

   65 nm SHA-256 ASIC synthesis study: clock gating, Multi-VT optimization, timing, area, and power analysis

   Verilog