2-Level Cache Controller on a RISC-V Core

A Verilog implementation of a 32-bit RV32I RISC-V processor integrated with a two-level cache hierarchy to reduce memory access latency and improve overall system performance.

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Overview

Modern processors rely on cache memories to bridge the speed gap between the CPU and main memory. This project implements a Single-Cycle RV32I RISC-V processor integrated with a 2-Level Cache Controller consisting of:

• L1 Direct-Mapped Cache
• L2 4-Way Set Associative Cache
• Write-Back Policy
• No Write-Allocate Policy
• Least Recently Used (LRU) Replacement

The design demonstrates how hierarchical caching improves processor performance by reducing average memory access time (AMAT).

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Features

• ✅ 32-bit RV32I Processor
• ✅ Single-Cycle Datapath
• ✅ Two-Level Cache Hierarchy
• ✅ Direct-Mapped L1 Cache
• ✅ 4-Way Set Associative L2 Cache
• ✅ LRU Replacement Algorithm
• ✅ Write-Back Policy
• ✅ No Write-Allocate Policy
• ✅ Main Memory Interface
• ✅ Verilog HDL Implementation
• ✅ Functional Verification using GTKWave

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System Architecture

+---------------------+
\|     RV32I CPU       |
+----------+----------+
|
v
+---------------------+
\|    L1 Cache         |
\| Direct Mapped       |
\| 64 Bytes            |
+----------+----------+
|
Miss
|
v
+---------------------+
\|    L2 Cache         |
\| 4-Way Set Associative|
\| 512 Bytes           |
+----------+----------+
|
Miss
|
v
+---------------------+
\|    Main Memory      |
\| 4 KB                |
+---------------------+