Electronics & Communications Engineer · Cairo University · Cairo, Egypt
I am a Digital IC Design Engineer bridging digital ASIC implementation with software engineering and AI/ML.
I have experience across the complete silicon flow, from translating complex DSP algorithms into RTL and integrating SoCs, to handling physical design (PnR) and timing analysis for clean tape-outs. Beyond traditional hardware, I build C/C++ software models for high-speed protocols and am passionate about applying machine learning to enhance EDA tools and build smarter platforms for silicon development.
- DSP Digital IC Trainee @ STMicroelectronics: Architected a dual-SoC wireless image processing system integrating Cortex-M0 cores, custom image processing accelerators, and a CNN hardware classifier via a 32-bit AHB bus. Verified the design using a UVM-based testbench (currently developing the VIP) and performed board-level testing on a Xilinx Virtex family FPGA.
- ASIC Implementation @ ICpedia: Designed and implemented a UCIe Die-to-Die Adapter Layer in SystemVerilog, executing the full RTL-to-GDSII flow, DFT insertion, and formal verification on TSMC 65nm.
- Software: Built a C++ golden reference model for the PCIe 6.0 Data Link Layer
- AI/ML Focus: Passionate about high-speed interconnects, EDA automation, hardware accelerators, and exploring how deep learning can be used to improve electronic design workflows.
