Computer Engineering @ NUST CEME · Pakistan
Computer Architecture · AI-Assisted Engineering · EDA · Research Engineering
Co-creator of ParetoCo · Founder & lead developer of ProGenEDA · Founder & lead developer at Type2Learn
Name : Muhammad Taha Bin Zaeem
Location : Pakistan
University : NUST CEME
Field : Computer Engineering
Build Mode : Computer architecture + EDA + AI + reproducible systems
North Star : Turn difficult technical ideas into testable engineering artifactsI work where hardware, architecture, AI, and engineering tooling overlap. I am especially interested in systems where AI cannot simply produce a convincing answer — the output has to survive a constraint solver, simulator, compiler, validation pipeline, or real user.
That has taken me from heterogeneous architecture design-space exploration and native EDA generation to MIPS, Verilog, research pipelines, and accessibility-focused AI products.
|
AI-assisted heterogeneous computer-architecture design-space exploration. ParetoCo combines Gecode-backed native constraint search, SDF workload modelling, and Pareto / multi-objective analysis across CPU, GPU, DSP, NPU, and accelerator design spaces. The AI layer helps translate natural-language intent into structured DSE models and interpret results, while deterministic native computation remains the source of truth for feasibility and trade-off evaluation. It also treats reproducibility as a first-class feature through sessions, snapshots, semantic diffs, Pareto-front evolution, and system-level analyses. Explore: Devpost · GitHub repository
|
AI-assisted EDA automation that produces editable engineering artifacts. Natural-language circuit intent is converted into a strict intermediate representation, checked, repaired where possible, and turned into native project output instead of stopping at a textual answer. The public library now contains 7,000+ Proteus circuits alone. Explore: Website · GitHub organization Why it matters: engineering AI should produce files that can actually be opened, inspected, edited, and tested.
|
|
Accessibility-first active learning designed for neurodivergent and neurotypical learners. Type2Learn turns course content into interactive learning where students actively respond through typing, speech, or other supported inputs instead of passively consuming material. Learners retain control over accessibility and presentation settings, while adaptation is bounded and consent-based. Explore: Website · GitHub organization Why it matters: AI-assisted learning should adapt without taking agency away from the learner.
|
Reproducibility-first pipelines for AI-assisted research. My research work emphasizes deterministic scripts, preserved source material, prompt templates, stored model outputs, metadata, checksums, environment records, and clear separation between model-generated interpretation and verifiable evidence. Why it matters: if an experiment depends on AI output, the evidence trail should be inspectable and repeatable.
|
ParetoCo
ProGenEDA
Type2Learn| Project | What it represents |
|---|---|
Mips_Chess_Engine |
Functional chess engine in MIPS assembly: board state, move validation, special rules, check/checkmate and a simple opponent |
CS-117-Project |
Single-cycle Verilog CPU with scalar and vector operations |
PROJECTINFINITY |
Local-first context/workflow system with structured project state, searchable data, approvals and reproducible handoffs |
autodecom |
Local binary-analysis workflow built around Ghidra and structured technical outputs |
FOP-Project |
C++ symbolic algebra solver with an AST-based simplification pipeline |
| Signal | Evidence |
|---|---|
| 🧩 I like architecture-level problems | heterogeneous DSE, constraint search, SDF workloads, CPU design |
| ⚙️ I care about real artifacts | native EDA projects, simulator-ready files, structured outputs, generated manifests |
| 🧪 I care about verification | deterministic search, validation, tests, snapshots, semantic diffs, reproducibility trails |
| 🧱 I am comfortable going low-level | MIPS assembly, Verilog/SystemVerilog, memory layout, processor architecture |
| 🤖 I use AI as part of systems, not as the whole system | bounded AI layers backed by deterministic engineering logic |
| 🌐 I can turn research ideas into products | ProGenEDA and Type2Learn as public, usable platforms |
| Project | What it represents |
|---|---|
| ParetoCo | AI-assisted heterogeneous architecture DSE with deterministic constraint search and Pareto analysis |
| ProGenEDA | AI-assisted EDA automation for editable native circuit project files |
| Type2Learn | Accessibility-first active learning with learner-controlled adaptation |
Mips_Chess_Engine |
A complete stateful application written in MIPS assembly |
CS-117-Project |
Processor design in Verilog with scalar and vector operations |
PROJECTINFINITY |
Local-first AI context and workflow architecture |
autodecom |
Structured binary-analysis automation |
| Now | Push architecture DSE and AI-assisted EDA toward stronger verification, evaluation, and real engineering use. |
| Next | Turn systems work into publishable computer-architecture / hardware-AI research with clean evidence trails. |
| Long Term | Work at the boundary of computer architecture, hardware, AI, and engineering systems without being trapped in one layer. |
rules:
- build first, then measure what actually works
- vague ideas are uncompiled specifications
- AI output is a proposal until deterministic checks agree
- document experiments before the context disappears
- keep artifacts editable, inspectable, and reproducible
- do not worship tools; make them serve the engineering goal