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video_stage: add the Orin-to-PC video transport - #1466
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AVS1 records, clock exchange, H.264 access-unit helpers and the frame correlator in video_stage_wire, and the Orin-side direct sender in video_stage_sender, with their tests. Plain C++ and POSIX sockets, built by BUILD_VIDEO_STAGE; no CUDA and no LiveKit. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com> Signed-off-by: Gareth Morgan <gmorgan@nvidia.com>
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November 10, 2026 22:23
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Closing as superseded: the camera path is now the camera_streamer architecture (SIPL/Argus sender, AVS1 over TCP, PC receiver and LiveKit bridge; see #1473-#1479). Not merged; the branch and commits are kept. 🤖 Generated with Claude Code |
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This PR is superseded by the camera_streamer PRs:
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Summary
The Orin-to-PC video transport, as plain C++ with no CUDA and no LiveKit. First of the video-stage PRs; each targets the one before it.
video_stage/wire: the AVS1 record codec (H.264 access units with frame number, stamps and source clock), the four-timestamp clock exchange, H.264 access-unit and SPS helpers, and the correlator that matches an encoded unit to its capture by stamp.video_stage/sender: the Orin-side sender of AVS1 records over a direct TCP link. It reconnects by itself, starts at a keyframe, drops to the next keyframe rather than block, and answers keyframe requests and clock exchanges.BUILD_VIDEO_STAGE=ON.Validation
video_stage_wire_tests(51 cases) andvideo_stage_sender_tests(17 cases) pass; they were run on the head of the next PR, which contains this one unchanged.Stacked on the Sensing timing PR (#1437); the next PR is the PC relay.
🤖 Generated with Claude Code