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6d48622
[TRTLLM-17033][feat] Engine, QSA and modeling_v2 catalog support for …
Wanli-Jiang Oct 19, 2026
e10d6c6
[TRTLLM-17033][feat] Qwen3.8-Flash-Next modeling_v2 target: MTP 1..7,…
Wanli-Jiang Oct 19, 2026
c8ed8cb
[TRTLLM-17033][test] Accuracy gates and test lists for the Qwen3.8-Fl…
Wanli-Jiang Oct 19, 2026
439b505
[TRTLLM-16460][perf] Shared kernels for the Qwen3.8-Flash-Next target…
Wanli-Jiang Oct 19, 2026
acafef1
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: attention ops
Wanli-Jiang Oct 19, 2026
ef3a736
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: Gated-DeltaNet ops an…
Wanli-Jiang Oct 19, 2026
d7b77d5
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: hyper-connection ops
Wanli-Jiang Oct 19, 2026
a14b0b9
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: MoE, GEMM, PLE and el…
Wanli-Jiang Oct 19, 2026
614965c
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: run the fast paths
Wanli-Jiang Oct 19, 2026
6e34769
[TRTLLM-16460][chore] Qwen3.8-Flash-Next target: remove dead paths an…
Wanli-Jiang Oct 19, 2026
370bcd0
[TRTLLM-17033][test] Run most qwen4_exp accuracy gates post-merge
Wanli-Jiang Oct 19, 2026
1f515cf
[TRTLLM-17033][fix] Give the beam-search admission stub the model eng…
Wanli-Jiang Oct 20, 2026
7c9e767
[TRTLLM-16460][fix] Qwen3.8-Flash-Next target: keep MTP verify steps …
Wanli-Jiang Oct 20, 2026
bf7b60f
[TRTLLM-16460][fix] Qwen3.8-Flash-Next target: gated norm sends a z t…
Wanli-Jiang Oct 20, 2026
66ab699
[TRTLLM-17033][chore] modeling_v2 routing: give each family's route t…
Wanli-Jiang Oct 20, 2026
7c8b176
[TRTLLM-16460][chore] Qwen3.8-Flash-Next target: own low_m_bf16_mm an…
Wanli-Jiang Oct 20, 2026
22c5e87
[TRTLLM-17033][test] Qwen3.8-Flash-Next tests: assert the decode over…
Wanli-Jiang Oct 20, 2026
37e2407
[TRTLLM-16460][chore] Qwen3.8-Flash-Next target: import the CuTe help…
Wanli-Jiang Oct 20, 2026
ebae095
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: one qsa_topk_expand_d…
Wanli-Jiang Oct 20, 2026
65f7c68
[TRTLLM-17033][fix] thop attention: FP8 context FMHA for a non-MLA NV…
Wanli-Jiang Oct 21, 2026
bf4dbeb
[TRTLLM-16460][perf] Qwen3.8-Flash-Next target: keep the second exper…
Wanli-Jiang Oct 21, 2026
b3e6c75
[TRTLLM-17033][fix] QSA cache manager: side-plane transfer roles inde…
Wanli-Jiang Oct 21, 2026
a8ce4e5
[TRTLLM-17033][test] Qwen3.8-Flash-Next accuracy gates: 26 cases down…
Wanli-Jiang Oct 21, 2026
078261b
[TRTLLM-17033][test] Qwen3.8-Flash-Next unit tests: certify the envel…
Wanli-Jiang Oct 21, 2026
8e12b66
[TRTLLM-17033][test] Qwen3.8-Flash-Next accuracy: six cases, each eng…
Wanli-Jiang Oct 21, 2026
c9288d9
[TRTLLM-17033][test] Qwen3.8-Flash-Next ops: at most three cells per …
Wanli-Jiang Oct 21, 2026
8094d42
[TRTLLM-17033][test] Qwen3.8-Flash-Next accuracy: acceptance floors f…
Wanli-Jiang Oct 21, 2026
257d5f0
[TRTLLM-17033][fix] PyExecutor admission: the model hook and its test…
Wanli-Jiang Oct 22, 2026
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4 changes: 4 additions & 0 deletions cpp/tensorrt_llm/thop/attentionOp.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1355,7 +1355,11 @@ void attention(torch::Tensor q, std::optional<torch::Tensor> k, std::optional<to
op->mRotaryEmbeddingLongMscale = rope_long_m_scale;
op->mRotaryEmbeddingMaxPositions = rope_max_positions;
op->mRotaryEmbeddingOriginalMaxPositions = rope_original_max_positions;
// Only the FP8 context FMHA kernels read an NVFP4 KV cache, whatever the output type; they do so on SM100-family
// GPUs only, so elsewhere an NVFP4 KV cache still fails the FP4 KV check in AttentionOp. MLA keeps its own NVFP4 KV
// handling (mUseNvfp4MlaKvCache, mFP8ContextMLA below) and must not pick this up.
op->mFP8ContextFMHA = is_fp8_out || is_fp4_out || (op->mKVCacheQuantMode.hasFp8KvCache() && use_paged_context_fmha)
|| (!is_mla_enable && op->mKVCacheQuantMode.hasFp4KvCache() && tensorrt_llm::common::isSM100Family())
|| use_sage_attn;
// SageAttention block sizes and quantization mode.
op->mSageAttnNumEltsPerBlkQ = static_cast<int>(sage_attn_num_elts_per_blk_q);
Expand Down
16 changes: 11 additions & 5 deletions tensorrt_llm/_torch/_experimental/modeling_v2/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -36,10 +36,15 @@ exists to catch.

The decision is one function, `route`, in the family's `routing.py`. It reads
the facts that fix which code runs -- the checkpoint's config shape, the
parallel mapping, the GPU's compute capability and the speculative-decoding
config -- and either returns a target class or raises `NoTarget` with the
reason in words. Tuning knobs such as `max_batch_size`, `max_num_tokens` and CUDA graph
settings are not routing inputs: they do not change which code runs, so a
parallel mapping, the GPU's compute capability, the speculative-decoding
config, the KV cache algorithm the engine will run with, and the engine choices
it derives from the `ModelConfig` and the LLM arguments it is also given
(qwen4_exp: MoE backend, recurrent-state cache dtype, prefill CUDA graph
backend) -- and either returns a target class or raises `NoTarget` with the
reason in words. A target declines what its
constructor would refuse, so that `auto` falls back instead of failing mid-build.
Tuning knobs such as `max_batch_size`, `max_num_tokens` and the CUDA graph
bucket lists are not routing inputs: they do not change which code runs, so a
target claims a configuration regardless of them. `require` therefore promises
that the target ran, not that a particular knob setting was measured. The model
loader decides when it is about to build the model, after the built-in model's
Expand Down Expand Up @@ -67,7 +72,8 @@ LLM(model=..., modeling_v2=...) -> ModelLoader
|
_router_index.py +-- architectures[0] -> routing module
models/<x>/routing.py +-- route(config, mapping, compute_capability,
| spec_config, kv_cache_quant_algo)
| spec_config, kv_cache_quant_algo,
| model_config, llm_args)
| -> target class, or NoTarget
|
config.modeling_v2_target = class
Expand Down
12 changes: 8 additions & 4 deletions tensorrt_llm/_torch/_experimental/modeling_v2/_router_index.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,12 @@
architecture family does.
* The routing module's ``route`` owns the rest of the decision as one
forward-reading tree over the facts that fix which code runs: the
checkpoint's config, the parallel mapping, the GPU's compute capability and
the speculative-decoding config. It returns the target class, or raises
:class:`NoTarget` with the reason in words. Reading that one file tells you
where any configuration lands.
checkpoint's config, the parallel mapping, the GPU's compute capability, the
speculative-decoding config and the KV-cache algorithm the engine will run
with. It also receives the ``ModelConfig`` and the LLM arguments, from which a
family derives any other engine choice its targets depend on. It returns the
target class, or raises :class:`NoTarget` with the reason in words. Reading
that one file tells you where any configuration lands.

Tuning knobs -- ``max_batch_size``, ``max_num_tokens``, CUDA graph settings --
are deliberately not routing inputs. They do not change which code runs, so a
Expand Down Expand Up @@ -195,6 +197,8 @@ def modeling_v2_resolve(config: "ModelConfig", llm_args: "TorchLlmArgs") -> Opti
_device_compute_capability(),
config.spec_config,
_kv_cache_quant_algo(config, llm_args),
model_config=config,
llm_args=llm_args,
)
except NoTarget as why:
if mode is ModelingV2Mode.REQUIRE:
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,21 @@ class FusedQkNormRope(OpWrapper):
"GEMMA_PREFILL_ATOL",
spec=dict(tokens=8192, gemma_prefill_band=True, **_QWEN_MAIN),
),
# The main rope run in place on qwen4_exp's fused input projection, whose
# row is [q | k | v | gate | index | pad] = 55 heads of 256: everything
# after k is passed as v heads, which only sets the row stride.
Cell(
why="qwen4_exp fused-row main rope, 1 token: 29 v heads only set the row stride",
spec=dict(tokens=1, **{**_QWEN_MAIN, "num_heads_v": 29}),
),
Cell(
why="qwen4_exp fused-row main rope, 128 tokens: decode at max concurrency",
spec=dict(tokens=128, **{**_QWEN_MAIN, "num_heads_v": 29}),
),
Cell(
why="qwen4_exp fused-row main rope, 8192 tokens: prefill, under GEMMA_PREFILL_ATOL",
spec=dict(tokens=8192, gemma_prefill_band=True, **{**_QWEN_MAIN, "num_heads_v": 29}),
),
Cell(
why="qwen4_exp index rope (mRoPE), 1 token: one k and one v head, the "
"narrowest layout; 5 warps of an 8-warp block",
Expand Down
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