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[Sim, Tests] Improve sim. Add sim tests. - #16

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uslsteen merged 10 commits into
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egorshamshura:add-tests-and-improve-sim
Oct 23, 2026
Merged

uslsteen merged 10 commits into
ProteusLab:masterfrom
egorshamshura:add-tests-and-improve-sim

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@egorshamshura
egorshamshura force-pushed the add-tests-and-improve-sim branch 3 times, most recently from 778da7a to b10499c Compare March 1, 2026 17:55
@egorshamshura
egorshamshura force-pushed the add-tests-and-improve-sim branch 5 times, most recently from 769dcfe to 5fdfd4f Compare March 12, 2026 07:41
Comment thread .clang-format
@derzhavin3016

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Pls separate formatting commits

Comment thread .github/workflows/build.yml
Comment thread cmake/QEMU.cmake
Comment thread sim_gen/ExecEngines/naive_interpreter.rb Outdated
@egorshamshura
egorshamshura force-pushed the add-tests-and-improve-sim branch from 29b2c66 to f00a942 Compare March 17, 2026 11:45
Comment thread test/SimTests/Common/RunTests.py Outdated
Comment thread test/SimTests/C/CImpl/qsort/qsort.c
Comment thread test/SimTests/Common/RunTests.py Outdated
Comment thread test/SimTests/Common/RunTests.py Outdated
Comment thread test/SimTests/SnippetBased/SnippetBasedImpl/InitTestGen.rb Outdated
Comment thread test/SimTests/SnippetBased/SnippetBasedImpl/InitTestGen.rb Outdated
Comment thread test/SimTests/SnippetBased/SnippetBasedImpl/InitTestGen.rb Outdated
@egorshamshura
egorshamshura force-pushed the add-tests-and-improve-sim branch from 9986ac2 to d6f4b6b Compare March 23, 2026 11:22
@egorshamshura
egorshamshura force-pushed the add-tests-and-improve-sim branch from e15114d to 8eed710 Compare March 23, 2026 11:36
egorshamshura and others added 3 commits March 24, 2026 07:44
qsort.c refers to 'See LICENSE for license details.' but the license
file was missing near the benchmark. The benchmark is adapted from
the riscv-tests benchmark suite, so add its BSD 3-Clause license.

Addresses review comment on PR ProteusLab#16.
Document what the ghcr.io/egorshamshura/protea-build image contains.

Addresses review comment on PR ProteusLab#16.
@uslsteen uslsteen self-assigned this Oct 23, 2026
@uslsteen
uslsteen merged commit 5bce161 into ProteusLab:master Oct 23, 2026
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@uslsteen uslsteen added the ISA description Architecture Description Language related task label Oct 27, 2026
@uslsteen uslsteen added simulator Simulation related task RISC-V Issue or task related to RISC-V architecture labels Oct 27, 2026
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3 participants