RV64F Support by uslsteen · Pull Request #22 · ProteusLab/Protea

uslsteen · 2026-07-02T22:06:19Z

No description provided.

TODO: 1. softfloat lib integration 2. Emition 3. Tests That's it

Also improved builder and encoding. Also integration of softfloat is questionable and I might have to look for better solution. TODO: 1. Finish builder 2. Implement Emitter. 3. Test. Optional: search for better building method. Current one is ugly, but it might be the optimal one, since softfloat doesn't provide cmake for some reason.

DONE: 1. Extra encoding formats needed for RV64F instructions. 2. Added some helper functions in scope.rb and cpp_gen.rb 3. Added emition of RV64F instrs. TODO: 1. Need to fix types for floating point temporaries. 2. Write tests. 3. Might need to refactor dsl implementation of this extension. Most methods can be generalized by adding their size as an attribute. It goes even further for Conversion instructions, because they all can be merged into one isntruction with 4 attributes. But this might become tidious in debug phase, so in my opinion, tests first, and then this changes.

Safety commit

TODO: 1. Do neg correctly. 2. Add rounding mode everywhere, for that I also need to change cpu_state emitter a bit. 3. Move most fp-relateed functions in separate module of emitter. 4. Tests.

…ions, added NaN checks that do not use isNaN from softfloat.

Also fixed a small bug in decorder, also started to write proposals (getting ready for mr)

* Exit code are passing from the exit syscall now * Introduced Control Status Register(s) read & write interfaces

uslsteen · 2026-07-20T20:13:25Z

+# float-to-int saturation match the RISC-V F/D spec (e.g. default NaN
+# 0x7FC00000, i32_fromNaN 0x7FFFFFFF) rather than the 8086/x86 semantics.
+file(GLOB SOFTFLOAT_PLATFORM_SRC
+  ${softfloat_SOURCE_DIR}/source/RISCV/*.c


Consider architecture specific.

uslsteen · 2026-07-20T20:15:35Z

        @emitter.emit_line("#{dst} = static_cast<#{Utility::HelperCpp.gen_small_type operation[:oprnds][0][:type]}>(#{src} << #{operation[:oprnds][3][:value]});")
      when :sysCall
        @emitter.emit_line('cpu.doExit();')
+      when :readCSR


Shall we accept it? @egorshamshura

That's not good to create separate operation for every external call

I think we need to add something like "externCall" or just "call" operation

uslsteen · 2026-07-20T20:21:58Z

+require 'Target/RISC-V/64I'
+require 'Target/RISC-V/64F'


I temporarily disabled RV 32 I, leaving only the 64-bit version for functional testing. How do we manage switching between 32/64-bit builds? @egorshamshura

uslsteen · 2026-07-20T20:23:02Z

        emitter.emit_line('// Function to stop the CPU execution')
        emitter.emit_line('void doExit() {')
        emitter.increase_indent
+        emitter.emit_line('m_exit_code = static_cast<int>(m_XRegs[10]);')


Let's leave it as is.

uslsteen · 2026-07-20T20:25:25Z

+    Instruction(:csrrw) {
+        encoding(*format_csr(0b1110011, 0b001))
+        asm { "csrrw {rd}, {csr}, {rs1}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, rs1)
+            rd[] = t
+        }
+    }
+
+    Instruction(:csrrs) {
+        encoding(*format_csr(0b1110011, 0b010))
+        asm { "csrrs {rd}, {csr}, {rs1}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, t | rs1)
+            rd[] = t
+        }
+    }
+
+    Instruction(:csrrc) {
+        encoding(*format_csr(0b1110011, 0b011))
+        asm { "csrrc {rd}, {csr}, {rs1}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, t & (rs1 ^ -1))
+            rd[] = t
+        }
+    }
+
+    Instruction(:csrrwi) {
+        encoding(*format_csri(0b1110011, 0b101))
+        asm { "csrrwi {rd}, {csr}, {zimm}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, zimm)
+            rd[] = t
+        }
+    }
+
+    Instruction(:csrrsi) {
+        encoding(*format_csri(0b1110011, 0b110))
+        asm { "csrrsi {rd}, {csr}, {zimm}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, t | zimm)
+            rd[] = t
+        }
+    }
+
+    Instruction(:csrrci) {
+        encoding(*format_csri(0b1110011, 0b111))
+        asm { "csrrci {rd}, {csr}, {zimm}" }
+        code {
+            t = readCSR(csr)
+            writeCSR(csr, t & (zimm ^ -1))
+            rd[] = t
+        }
+    }
+end


Is it okay, @derzhavin3016 , @egorshamshura ?

uslsteen · 2026-07-20T20:32:48Z

+  INT_INFO = {
+    i32: 'int32_t',
+    u32: 'uint32_t',
+    i64: 'int64_t',
+    u64: 'uint64_t'
+  }.freeze


Let's move into more generic part.

uslsteen · 2026-07-20T20:35:46Z

@doushe821 remove please all "PROPOSAL" comments.

… changes in value.rb and builder.rb

derzhavin3016 · 2026-07-24T20:27:01Z

+        @emitter.emit_line("uint64_t v = #{src};")
+        @emitter.emit_line('uint64_t sign = v >> 63;')
+        @emitter.emit_line('uint64_t exp  = (v >> 52) & 0x7FF;')
+        @emitter.emit_line('uint64_t frac = v & 0xFFFFFFFFFFFFFULL;')
+        @emitter.emit_line('uint32_t r = 0;')
+        @emitter.emit_line('')
+        @emitter.emit_line('if (exp == 0x7FF) {')
+        @emitter.emit_line('  if (frac == 0) r = sign ? (1u << 0) : (1u << 7);')
+        @emitter.emit_line('  else r = (frac & (1ULL << 51)) ? (1u << 9) : (1u << 8);')
+        @emitter.emit_line('}')
+        @emitter.emit_line('else if (exp == 0) {')
+        @emitter.emit_line('  if (frac == 0) r = sign ? (1u << 3) : (1u << 4);')
+        @emitter.emit_line('  else r = sign ? (1u << 2) : (1u << 5);')
+        @emitter.emit_line('}')
+        @emitter.emit_line('else {')
+        @emitter.emit_line('  r = sign ? (1u << 1) : (1u << 6);')
+        @emitter.emit_line('}')
+        @emitter.emit_line('')
+        @emitter.emit_line("#{dst} = r;")


Seems like this code should not be generated

Just to clarify, do you propose making a new file in sim_lib directory in which architecture specific implementations will be stored? Maybe it would be better to still generate it but move it to a separate .rb file and include this file conditionally. E.g. make a function f64_classify_general and make every file with architecture-specific implementation implement their own version and then require needed file based on architecture flag or something like that.

Done, but needs review, because I've modified quite a bit with the last commit. (decided to add interface for architecture-specific implementations to non-generated C++ code)

Removed generation of classify instructions from ruby files, moved them to riscv_arch_ops.cc. Implemented interface class arch_ops.hh. Added architecture specifying field to IR.yaml (was hardcoded previously).

uslsteen

I suggest moving the common FPU API to the Generic/ directory and the architecture-specific code to the corresponding directories.

…ded fpu everywhere)

doushe821 and others added 15 commits March 10, 2026 20:22

[DSL] Finished encoding description

12df70b

TODO: 1. softfloat lib integration 2. Emition 3. Tests That's it

[Emitter] Minor progress in fixing type issues

d8558a1

Safety commit

[Emitter] Described typing for almost all instructions.

95b2957

TODO: 1. Do neg correctly. 2. Add rounding mode everywhere, for that I also need to change cpu_state emitter a bit. 3. Move most fp-relateed functions in separate module of emitter. 4. Tests.

[DSL] Added factorization over rounding mode, fixed min/max/neg funct…

e3de017

…ions, added NaN checks that do not use isNaN from softfloat.

[Tests][Decoder] Added unit tests for rv64f.

041256b

Also fixed a small bug in decorder, also started to write proposals (getting ready for mr)

[MR] Added more proposal comments

21295f5

[MR] Reverted codestyle changes

56a7c54

[MR] Separated fp-related functions from the rest of the dsl

16c6237

[Minor changes] removed typos

72cb1fd

Introduced RV64I extension (XLEN=64)

4ad58e9

FMOV truncate bug found & fixed

2d3b54f

Introduced exit code & read/write CSR

95f0ef2

* Exit code are passing from the exit syscall now * Introduced Control Status Register(s) read & write interfaces

RISC-V Nan fixed

f1b3e2b

uslsteen assigned doushe821 Jul 2, 2026

uslsteen mentioned this pull request Jul 2, 2026

Implemented RV64F extension. #18

Closed

uslsteen added help wanted Extra attention is needed dsl long-term labels Jul 2, 2026

This was linked to issues Jul 2, 2026

RV64 Support #4

Open

RV64I Support #5

Open

RV64F Support #7

Open

uslsteen requested a review from egorshamshura July 2, 2026 22:10

uslsteen commented Jul 20, 2026

View reviewed changes

doushe821 added 2 commits July 20, 2026 23:55

[COSMETIC] Removed all # PROPOSAL comments and reverted autoformatter…

01d5616

… changes in value.rb and builder.rb

[COSMETIC] Removed last autoformatter artifacts

2f20c1d

derzhavin3016 reviewed Jul 24, 2026

View reviewed changes

Comment thread cmake/softfloat.cmake Outdated

derzhavin3016 reviewed Jul 24, 2026

View reviewed changes

doushe821 added 2 commits August 14, 2026 15:57

Pinned softfloat version

93f50e1

Added architecture specific function implementation support.

b27676e

Removed generation of classify instructions from ruby files, moved them to riscv_arch_ops.cc. Implemented interface class arch_ops.hh. Added architecture specifying field to IR.yaml (was hardcoded previously).

uslsteen commented Sep 10, 2026

View reviewed changes

Comment thread sim_lib/arch_ops.hh Outdated

[COSMETIC] Renamed helper files and classes to more specfic names (ad…

bfe12c7

…ded fpu everywhere)

This was referenced Sep 24, 2026

RV64F Support #7

Open

RV64I Support #5

Open

Conversation

uslsteen commented Jul 2, 2026

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

egorshamshura Sep 2, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

uslsteen commented Jul 20, 2026

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

uslsteen left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Reviewers

Uh oh!

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

egorshamshura Sep 2, 2026 •

edited

Loading