[bsp][esp32-c6] add ESP32-C6-DevKitC-1 support - #11836
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cms19859230182-lang wants to merge 9 commits into
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cms19859230182-lang wants to merge 9 commits into
cms19859230182-lang wants to merge 9 commits into
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Add bsp/ESP/ESP32_C6. Default image is GPIO, UART0 and ADC. The C6 IDF sources are not in RT-Thread-packages/esp-idf yet.
cms19859230182-lang
requested review from
kurisaW and
supperthomas
as code owners
September 24, 2026 17:30
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BSP
BSP: ESP32
📌 Code Review Assignment🏷️ Tag: workflowReviewers: @Rbb666 @kurisaW @supperthomas Changed Files (Click to expand)
📊 Current Review Status (Last Updated: 2026-09-27 17:08 CST)
📝 Review Instructions
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Contributor
Author
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中秋快乐呀扎人们 |
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clang-format the files the format check rejected. Fetch the C6 scons branch when the downloaded ESP-IDF package has no C6 target. Patch the CH32V20x SDK under libraries so a D6 build no longer calls Exit().
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Contributor
Author
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@Rbb666 额度没啦，我发的另外一个也是这样 |
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我换个轻量的AI先扫一下 |
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Copilot review overview
🟡 Changes recommended
Unresolved critical portability and macro issues remain, along with configuration and build reproducibility inconsistencies.
Review effort: Lite
Findings: 2
Open (10)
| portEXIT_CRITICAL(mux); \ | ||
| } \ | ||
| }) | ||
| #define portTRY_ENTER_CRITICAL_SAFE(mux, timeout) portENTER_CRITICAL_SAFE(mux, timeout) |
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| double ceil(double i) | ||
| { | ||
| i = i; | ||
| return i; |
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| # CONFIG_BSP_USING_ADC is not set | ||
| # CONFIG_BSP_USING_PWM is not set |
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| dest = os.path.join(libraries_path_prefix, 'ESP-IDF-latest') | ||
| sc = os.path.join(dest, 'SConscript') |
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| subprocess.check_call([ | ||
| 'git', 'clone', '--depth', '1', '--branch', 'bsp/esp32c6-scons', | ||
| 'https://github.com/cms19859230182-lang/esp-idf.git', tmp, |
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| config BSP_BOARD_ESP32C6_DEVKITC1 | ||
| bool "ESP32-C6-DevKitC-1" |
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| if (!enabled) | ||
| { | ||
| return RT_EOK; | ||
| } | ||
|
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| } | ||
| esp_rom_delay_us(2); | ||
| } | ||
| raw_pin = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff; |
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| #define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, | ||
| #define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1 | ||
| #define CONFIG_SOC_RTCIO_WAKE_SUPPORTED 1 |
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| candidates = [ | ||
| os.path.join(SDK_ROOT, 'packages', 'CH32V20x-SDK-for-RTT', 'SConscript'), | ||
| os.path.join(libraries_path_prefix, 'ch32v20x_sdk-latest', 'SConscript'), | ||
| ] | ||
| for sc in candidates: |
Keep the IDF tree on the reviewed commit, and stop the ADC and critical-section paths from reporting success when they did not.
Contributor
Author
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ok我re完了 |
Rbb666
reviewed
Sep 27, 2026
CPU lines 3 and 4 never latch an enable, so copying the handler left the non-IRAM mask on the old line. Reserve those lines and let the allocator write the mask and the route together. The C6 oneshot registers are shared, so one mutex covers enable and convert.
GPIO, UART0 and ADC1 have been read on the DevKitC-1. Radios and the untested buses stay marked unsupported.
GPIO7 shorted to GPIO2 returned 0xA5000000 for a sent 0xA5, so the table does not mark SPI supported.
Contributor
Author
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ok搞定了，刚刚编码乱掉了 |
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拉取/合并请求描述：(PR description)
为什么提交这份PR (why to submit this PR)
ESP32-C6-DevKitC-1 has no BSP in the mainline tree. The module is ESP32-C6-WROOM-1, RISC-V, revision v0.2, 8MB flash.
RT-Thread-packages/esp-idfhas not been updated since 2023-11-26 and has no C6 sources, sopkgs --updatecannot build this board.你的解决方案是什么 (what is your solution)
Add
bsp/ESP/ESP32_C6. UART0 is GPIO16/GPIO17 on the DevKitC-1 UART USB port (CP210x). The default image enables GPIO, UART0 and ADC.builtin_imgs/bootloader.binis an ESP32-C6 bootloader. Do not reuse the ESP32-C3 bootloader. Flash is DIO, 8MB, 80MHz. The application offset is0x10000.C6 scons sources are on https://github.com/cms19859230182-lang/esp-idf/tree/bsp/esp32c6-scons (RT-Thread-packages/esp-idf#17). Clone that branch to
packages/ESP-IDF-latest.On this chip, PLIC enable for CPU interrupts 3 and 4 does not stick. The BSP reserves those two lines at startup and clears
midelegbefore the allocator routes the devices.Shared driver changes:
drv_gpio.c:pininput mode no longer falls through into open-drain.drv_uart.c: C6 UART clock isUART_SCLK_DEFAULT.drv_adc.c: C6 reads ADC1 from the registers. GPIO1 read 2167 on GND and 4095 on 3.3V. There is no calibration, so ground is not 0.Verified on ESP32-C6-DevKitC-1 with Espressif riscv32-esp-elf GCC 11.2.0:
msh.helpandversionanswer.versionis 5.3.1.list timercurrent tickincreases.freetotal 76704, used heap about 68904 free.0xA5and read0xA5000000. That is not a single-byte match, so SPI stays unsupported. The test is not in the default image.BSP_ENABLE_GDBSTUBon, a store to address 4 printsEntering gdb stub now.GDB stops inmainat PC0x42001c8c, the same value as MEPC. The default image leaves this switch off.请提供验证的bsp和config (provide the config and bsp)
BSP:
bsp/ESP/ESP32_C6.config: default is GPIO, UART0 and ADC. I2C, SPI, PWM, Wi-Fi, BLE and GDBStub are off.
action:
当前拉取/合并请求的状态 Intent for your PR
必须选择一项 Choose one (Mandatory):
代码质量 Code Quality：
我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up