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3 changes: 3 additions & 0 deletions bsp/qemu-virt64-riscv/SConstruct
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,9 @@ rtconfig.ARCH='risc-v'
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)

if not GetDepend('RT_USING_CPLUSPLUS'):
env['LINKFLAGS'] = env['LINKFLAGS'].replace(' -lsupc++', '')

stack_size = 4096

if GetDepend('RT_USING_SMART'):
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3 changes: 3 additions & 0 deletions bsp/qemu-virt64-riscv/rtconfig.py
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,9 @@
OBJCPY = PREFIX + 'objcopy'

DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64 '
# Optional Picolibc toolchain; leave the default libc selection unchanged.
if os.getenv('RTT_PICOLIBC_SPECS'):
DEVICE += '--specs=' + os.environ['RTT_PICOLIBC_SPECS'] + ' '
CFLAGS = DEVICE + '-ffreestanding -flax-vector-conversions -Wno-cpp -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fdiagnostics-color=always'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__ '
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static'
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