Replace IP_space.cpp/L2_space.cpp #ifdef cascades with declarative dispatch tables

[dor-forer]

Summary

Stacked on #1004 (R1). Replaces the #ifdef-nested runtime feature-check cascades in every GetDistFunc-per-combo function in IP_space.cpp/L2_space.cpp with a declarative dispatch table.

• New DispatchTier<DistType> row struct (dispatch_tier.h): a CPU-feature predicate, a dimension floor (min_dim), an alignment hint (alignment_chunk_elems), and the existing (unchanged) Choose_* function for that tier.
• New pure select_tier_index(features, dim, rows) helper: only does predicate/min_dim comparisons, never calls a row's chooser. This is the key safety property — it never touches an arch-specific translation unit, so it's safe to call with fabricated Features values regardless of what the host CPU actually supports, unlike the full GetDistFunc/Choose_* path.
• The actual per-combo tables (IP_FP32_DispatchTable, Cosine_INT8_DispatchTable, etc. — 21 total) live in two new headers (IP_dispatch_tables.h, L2_dispatch_tables.h) as inline constexpr — required, not stylistic: these variables need their full initializer visible in every TU that reads them, and both GetDistFunc and test_spaces.cpp need to see the exact same table object, not a hand-duplicated copy that could drift.
• GetDistFunc names/signatures are unchanged.
• The BF16 big/little-endian split isn't a tier-selection concern and stays a special-cased branch before the table is ever consulted, in both files.

Two documented asymmetries preserved (verified by dedicated tests, not just re-derived from memory)

• Cosine_INT8/Cosine_UINT8's AVX-512 tier deliberately never sets an alignment hint (alignment_chunk_elems=0) — the extra norm float shifts effective alignment in a way the original code skips computing, to avoid complexity. There is no L2 mirror: L2_INT8/L2_UINT8 set alignment normally.
• IP_BF16 has an AVX512BF16_VL tier that L2_BF16 never had in the original cascade (L2 only ever dispatched BF16 to AVX512BW_VBMI2 on that rung).

Verification

• Compile: IP_space.cpp, L2_space.cpp, test_spaces.cpp all compile clean standalone (-Werror -Wall -std=gnu++20). grep -c "if (features\." on both _space.cpp files is 0 — confirms every cascade was actually converted, not left partially done.
• Unit tests: make unit_test CTEST_ARGS="-R Spaces" — 1452/1452 passed, 0 failed. Includes the existing exhaustive real-hardware *OptFuncs suites (unchanged, now the regression oracle for full GetDistFunc behavior) plus 10 new SpacesDispatchTierTest cases: no-feature scalar fallback, overlapping-feature priority, missing-top-feature fallthrough, min_dim-1/min_dim/min_dim+1 boundaries, and both documented asymmetries above — all exercised against the real production tables via select_tier_index with fabricated features (safe, since it never calls a chooser).
• Benchmark smoke test: bm_spaces_sq8_fp32 --benchmark_filter=AVX2 runs clean end-to-end (IP/L2/Cosine all correctly dispatch through the new table to AVX2/AVX2_FMA). Note: this dev box's compiler can target AVX512F but the actual host CPU doesn't have it — bm_spaces_fp32 --benchmark_filter=AVX512F correctly errors with "requires AVX512F, which is not available" rather than crashing, same SIGILL-safety property the tests rely on.
• Like R1, the ARM-only tiers in these tables are converted with the same verified pattern but unverified on this box (no aarch64 toolchain) — needs a real ARM build + test pass before merge.

Test plan

• make unit_test CTEST_ARGS="-R Spaces" — 1452/1452 passed
• Standalone compile of IP_space.cpp/L2_space.cpp/test_spaces.cpp
• make check-format
• Benchmark smoke test (AVX2 tiers, real hardware)
• Real ARM/NEON/SVE compile + test pass (no aarch64 toolchain on this dev box)