Remove patches that conflict with upstream review comments; submit optimized patches later. - #43
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XYenChi wants to merge 20 commits into
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Remove patches that conflict with upstream review comments; submit optimized patches later.#43XYenChi wants to merge 20 commits into
XYenChi wants to merge 20 commits into
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* Add RISC-V 64 BLOCK_LIST * Skip long time testcase Co-authored-by: Cursor <cursoragent@cursor.com>
* Add riscv64 ci with PR
⭐ Run Main Diff base and head Push to riscv From https://github.com/RuyiAI-Stack/pytorch * branch riscv -> FETCH_HEAD fatal: Not a valid object name origin/main Error: ❌ Failure - Main Diff base and head Error: exit status 128
* mklnn is unavailable on RISC-V * Remove test_cpu_select_algorithm from block_list * Fix block list format
These cases are too slow on riscv64, adding them to here simply Drop test_torch from the list because it is one core case
for action, these yaml must be merged first then take effect, so merge it skipping ci
bytes_to_scalar previously round-tripped raw bytes through Python
float/complex values (via ctypes) before constructing the tensor. This
loses NaN bit patterns on architectures (such as RISC-V) that
canonicalize NaNs in floating-point loads/conversions, causing
test_bytes_to_scalar_cpu_{float32,float64,complex64,complex128} to
fail with mismatched storage bytes.
Construct the scalar tensor by reinterpreting the raw bytes as the
target dtype via tensor.view(dtype), so all input bit patterns
(including NaN payloads) are preserved exactly.
Test Plan:
python test/test_torch.py TestTorchDeviceTypeCPU.test_bytes_to_scalar_cpu_complex64
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变更说明 / Summary
Remove patch and will push better version according to upstream's suggestion.
关联 Issue / Related issue
验证方式 / Validation
检查清单 / Checklist