RISC-V Vector Extension (RVV) support for ATen - #46
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* Add RISC-V 64 BLOCK_LIST * Skip long time testcase Co-authored-by: Cursor <cursoragent@cursor.com>
* Add riscv64 ci with PR
⭐ Run Main Diff base and head Push to riscv From https://github.com/RuyiAI-Stack/pytorch * branch riscv -> FETCH_HEAD fatal: Not a valid object name origin/main Error: ❌ Failure - Main Diff base and head Error: exit status 128
* mklnn is unavailable on RISC-V * Remove test_cpu_select_algorithm from block_list * Fix block list format
These cases are too slow on riscv64, adding them to here simply Drop test_torch from the list because it is one core case
bytes_to_scalar previously round-tripped raw bytes through Python
float/complex values (via ctypes) before constructing the tensor. This
loses NaN bit patterns on architectures (such as RISC-V) that
canonicalize NaNs in floating-point loads/conversions, causing
test_bytes_to_scalar_cpu_{float32,float64,complex64,complex128} to
fail with mismatched storage bytes.
Construct the scalar tensor by writing the raw bytes directly into its
untyped storage so all input bit patterns (including NaN payloads) are
preserved exactly.
RISC-V converts non-finite floats to integers by saturating: -inf -> min, inf/nan -> max for wider int types. Add IS_RISCV64 flag and RISC-V-specific reference values. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
for action, these yaml must be merged first then take effect, so merge it skipping ci
Signed-off-by: Fei Zhang <zhangfei@iscas.ac.cn> Co-authored-by: Chung-Lin Tang <cltang@baylibre.com>
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嗨, 我是软件所的张飞, 我之前有做过 pytorch 相关工作:
pytorch#127867
pytorch#143979
pytorch#166602
pytorch#135570
其中, pytorch#135570 的工作并没有受上游太重视且审核缓慢, 希望这个 PR 内容能够合并到 RuyiAI, , 希望随着你们的 ci 等推进一并合并到上游。
变更说明 / Summary
为 pytorch vec 后端添加了
rvv后端支持, 且该 PR 已适配到最新的上游代码关联 Issue / Related issue
下面是提交给上游的pr(均未合并), 因长时间未改动已被关闭, 其中一个是联合
RISE提交的:pytorch#175746
pytorch#135570
验证方式 / Validation
gcc: gcc-15
平台: sg2044
vec库功能测试:
./build/bin/vec_test_all_types_RVV, 结果均已通过:检查清单 / Checklist