Add RISC-V Vector (RVV) CPU capability - #48
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* Add RISC-V 64 BLOCK_LIST * Skip long time testcase Co-authored-by: Cursor <cursoragent@cursor.com>
* Add riscv64 ci with PR
⭐ Run Main Diff base and head Push to riscv From https://github.com/RuyiAI-Stack/pytorch * branch riscv -> FETCH_HEAD fatal: Not a valid object name origin/main Error: ❌ Failure - Main Diff base and head Error: exit status 128
* mklnn is unavailable on RISC-V * Remove test_cpu_select_algorithm from block_list * Fix block list format
These cases are too slow on riscv64, adding them to here simply Drop test_torch from the list because it is one core case
bytes_to_scalar previously round-tripped raw bytes through Python
float/complex values (via ctypes) before constructing the tensor. This
loses NaN bit patterns on architectures (such as RISC-V) that
canonicalize NaNs in floating-point loads/conversions, causing
test_bytes_to_scalar_cpu_{float32,float64,complex64,complex128} to
fail with mismatched storage bytes.
Construct the scalar tensor by writing the raw bytes directly into its
untyped storage so all input bit patterns (including NaN payloads) are
preserved exactly.
RISC-V converts non-finite floats to integers by saturating: -inf -> min, inf/nan -> max for wider int types. Add IS_RISCV64 flag and RISC-V-specific reference values. Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
for action, these yaml must be merged first then take effect, so merge it skipping ci
Add a FindRVV module that probes -march=rv64gcv support, register it in Dependencies.cmake, and emit an RVV capability in Codegen.cmake. Wire RVV through the DispatchStub plumbing (enum member, dispatch pointer, REGISTER_RVV_DISPATCH, and runtime detection via cpuinfo_has_riscv_v) so RVV-compiled kernels are selected at runtime, mirroring the existing SVE/VSX/ZVECTOR handling. Every addition is guarded by HAVE_RVV_CPU_DEFINITION and is inert on non-RISC-V builds. Test Plan: The RISC-V build runs on sg2044. PASS the CI core test. Authored with AI assistance.
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Add a FindRVV module that probes -march=rv64gcv support, register it in Dependencies.cmake, and emit an RVV capability in Codegen.cmake. Wire RVV through the DispatchStub plumbing (enum member, dispatch pointer, REGISTER_RVV_DISPATCH, and runtime detection via cpuinfo_has_riscv_v) so RVV-compiled kernels are selected at runtime, mirroring the existing SVE/VSX/ZVECTOR handling.
Every addition is guarded by HAVE_RVV_CPU_DEFINITION and is inert on non-RISC-V builds.
Test Plan:
The RISC-V build runs on sg2044. PASS the CI core test.
Authored with AI assistance.
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