Currently we have no means to capture Interrupt Mode correctly, which will break snapshots and makes it impossible to change+restore the interrupt mode when entering NMI.
Since we cannot read the IM, the FPGA needs to capture execution of the IM instructions and latch the values so we can read them afterwards. We can use unused bits in the FIFO status register to avoid using extra registers, this will require minor changes to the current ASM code which tests for "not zero" values to figure if FIFO is empty.
Currently we have no means to capture Interrupt Mode correctly, which will break snapshots and makes it impossible to change+restore the interrupt mode when entering NMI.
Since we cannot read the IM, the FPGA needs to capture execution of the IM instructions and latch the values so we can read them afterwards. We can use unused bits in the FIFO status register to avoid using extra registers, this will require minor changes to the current ASM code which tests for "not zero" values to figure if FIFO is empty.