Generated from committed benchmark_results/**/*.jsonl records.
Latest record: pass from source a93dc8141c40.
Latest passing RTL IPC: 2.025105
Latest passing run: 1 iteration(s), 188406 cycles, 381542 committed instructions.
Latest record: pass from source 57e2b815643c.
Latest passing RTL IPC: 2.549098
Latest passing run: 1024 elements x 3 runs, 1352868 cycles, 3448593 committed instructions.
Bandwidth is measured over the full RTL run. L1 counts accepted D-cache payload bytes; L2/L3 count accepted data-source cache-line request bytes; DRAM counts accepted external AXI payload bytes.
| Level | Total bytes/cycle | Read bytes/cycle | Write bytes/cycle | Total bytes | Measurement point |
|---|---|---|---|---|---|
| L1 | 1.437975 |
0.737141 |
0.700834 |
1945391 |
core-side D-cache payload |
| L2 | 0.056011 |
0.056011 |
0.000000 |
75776 |
L1D to L2 cache-line requests |
| L3 | 0.019065 |
0.019065 |
0.000000 |
25792 |
data-source L2 to L3 cache-line requests |
| DRAM | 0.025215 |
0.025215 |
0.000000 |
34112 |
external AXI payload |
Regenerate:
python3 harness/plot_benchmark_history.py coremark
python3 harness/plot_benchmark_history.py stream