A small, deterministic, Turing-complete virtual machine with a register-based instruction set and a flat, byte-addressable memory. SPEC.md is the normative specification — all behavior not described there is undefined.
- 32 general-purpose registers (
r0zero register,sp/fp), 32-bit little-endian words, 4 condition-code flags. - Two instruction formats (R-form: 4 bytes, I-form: 8 bytes) with arithmetic, memory, control flow, stack, and syscall groups.
- Unbounded abstract memory; concrete v1 encoding uses 32-bit addresses mapped lazily.
- Bytecode file format with optional 12-byte
"ODIN"header and entry point. - Deterministic execution with a defined trap model (invalid opcode, misalignment, division by zero, etc.).
- Turing completeness argued in §12 (RAM / direct TM / counter-machine simulations).
Specification-only (v1). No reference implementation or assembler yet.
SPEC.md # Normative specification v1 (instruction set, formats, traps, ABI)
| Topic | Section |
|---|---|
| Virtual machine overview | SPEC.md §1–§3 |
| Instruction formats | SPEC.md §4 |
| Instruction set reference | SPEC.md §6 |
| Bytecode file format | SPEC.md §8 |
| Traps and errors | SPEC.md §9 |
| System call ABI | SPEC.md §11 |
| Turing-completeness proof | SPEC.md §12 |
| Example programs | SPEC.md §13 |
| Extensibility & versioning | SPEC.md §14 |