All pull requests

Pull requests

• LLVM emitter: emit fixed parameter types in variadic call types

  #338·jorgsowa opened Nov 14, 2026Contributor·

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• Fix SWITCH of 8/16-bit integers on AArch64

  #337·jorgsowa opened Nov 14, 2026Contributor·

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• x86_64: always emit mov for 32->64 ZEXT

  #336·jorgsowa opened Nov 14, 2026Contributor·

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• C emitter: avoid UB in ROL/ROR with a zero rotate count

  #335·jorgsowa opened Nov 13, 2026Contributor·

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• C emitter: emit string constants as uintptr_t

  #333·jorgsowa opened Nov 12, 2026Contributor·

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  3

• Validate generated C and LLVM code in test-ci

  #329·jorgsowa opened Nov 10, 2026Contributor·

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  1

• Check operand types

  #324·jorgsowa opened Nov 10, 2026Contributor·

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  7

• Don't use a bound spill slot that the value's live range may overwrite

  #313·iliaal opened Nov 6, 2026Contributor·

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• Fold CTLZ(ZEXT(x)) - (dst_bits - src_bits) into ZEXT(CTLZ(x))

  #274·jorgsowa opened Oct 27, 2026Contributor·

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  4

• test: Add C and LLVM emitter roundtrip tests to CI

  #273·jorgsowa opened Oct 27, 2026Contributor·

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• Fix GCM sinking of bound nodes past an OSR ENTRY

  #257·iliaal opened Oct 24, 2026Contributor·

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  5

• Fix narrow (8/16-bit) integer handling on AArch64

  #237·jorgsowa opened Oct 14, 2026Contributor·

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  2

• Add riscv64 backend with a hand-written binary encoder

  #178·mengzhuo opened Aug 13, 2026·

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  29

• RISC-V code generator (binary-encoding, hooked into ir_match/ir_ra/ir_emit_code)

  #174·steven-studio opened Jul 21, 2026·

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  4

• RISC-V code generator (assembly-text emitter, not JIT machine-code path) — worth pursuing this direction?

  #169·steven-studio opened Jul 14, 2026·

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  3

• Improve RLOAD/RSTORE handling

  #133·arnaud-lb opened Mar 27, 2026Contributor·1 task·

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  12

• A few trivial improvements for code readability

  #35·stkeke opened May 20, 2023·

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• Improve cross-compilation

  #30·jserv opened May 7, 2023Contributor·

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  1