Add SVE2 optimizations for SynetMergedConvolution16b Cdc/Cd/Dc - #836
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Port MergedConvolution16b Input/Depthwise/Output kernels to SVE2/SVE-BF16 for ARM/ARM64, wire Init dispatch and tests, update VS project files, and document the change in release 7.2.165. Co-authored-by: Ihar Yermalayeu <ermig1979@gmail.com>
Avoid arrays/pointers of svfloat32_t (invalid for SVE sizeless types), pass bias/params by value, and keep Float32ToBFloat16 local to prevent redefinition with other SVE2 16b kernels. Co-authored-by: Ihar Yermalayeu <ermig1979@gmail.com>
ermig1979
marked this pull request as ready for review
August 10, 2026 11:13
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Summary
SynetMergedConvolution16bCdc,SynetMergedConvolution16bCd, andSynetMergedConvolution16bDc(Input/Depthwise/Output kernels usingsvbfdot_f32where applicable).SimdSynetMergedConvolution16bInitdispatch andTest::SynetMergedConvolution16bAutoTestfor SVE2.prj/vs2022/Sve2.vcxproj(.filters)and document NEON/SVE2 MergedConvolution16b entries under release 7.2.165 indocs/2026.html.Validation
SimdandTestfor aarch64 with-DSIMD_SVE2=ON(aarch64-linux-gnu-g++,-march=armv9-a+sve+sve2+i8mm+bf16); both targets built successfully../Test "-r=.." -fi=SynetMergedConvolution16b -tt=1 -ts=1).