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feat(rvv): add vector arithmetic and PQ distance table kernels - #5655

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Xlawy:feat/rvv-fvec-pq-distance-dispatch
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Xlawy wants to merge 2 commits into
facebookresearch:mainfrom
Xlawy:feat/rvv-fvec-pq-distance-dispatch

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@Xlawy

@Xlawy Xlawy commented Sep 19, 2026

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Summary

On RISC-V, fvec_add, fvec_sub and compute_PQ_dis_tables_dsub2 are dispatched through with_simd_level_256bit, whose level mask (AVAILABLE_SIMD_LEVELS_AVX2_NEON) has no RISCV_RVV bit. RVV hosts therefore fall back to the scalar NONE implementation.

This PR adds native RVV kernels for these functions and fixes the dispatch, following the same vector-length-agnostic approach as the RVV kernels already in the tree: the kernels are __riscv_vsetvl-based (m8) and adapt to any VLEN at runtime instead of assuming a fixed vector width.

Changes

  • Add RVV kernels in faiss/utils/simd_impl/distances_rvv.cpp:
    • fvec_add (vector + vector and vector + scalar)
    • fvec_sub
    • compute_PQ_dis_tables_dsub2 (PQ distance tables for dsub = 2, both L2 and inner product). Each product/square is rounded before the final add — like the NONE implementation and unlike a fused vfmacc — so the tables are bit-identical to the scalar ones.
  • Add AVAILABLE_SIMD_LEVELS_BASE_NO_AVX512 mask in faiss/impl/simd_dispatch.h (BASE minus AVX512: functions with NONE/AVX2/ARM_NEON/RISCV_RVV implementations but no 512-bit specialization, so AVX512 machines keep the AVX2 path).
  • Route the four dispatchers in faiss/utils/distances_dispatch.h through the new mask.
  • Enable the PQ dsub = 2 distance table path in ProductQuantizer::compute_distance_tables / compute_inner_prod_tables on RISC-V (COMPILE_SIMD_RISCV_RVV), previously guarded to AVX2/ARM_NEON only. No behavior change on other platforms.

Performance

Measured on SG2044 (64-core RISC-V, RVV 1.0), Faiss C++ benchmark suite, rcq-search case:

Metric Baseline Patched Change
instructions 7.25 T 6.87 T -5.2%
cycles 4.60 T 4.30 T -6.5%
wall time 238.1 s 223.6 s -6.1%
branches 334.6 G 305.0 G -8.8%

fvec_add hotspot in perf record drops from 1.06% (scalar NONE) to 0.18% (RVV) of samples.

Correctness

  • sq-accuracy reconstruction errors bit-identical to baseline on all 9 quantizer types, ndiff_for_idempotence=0.
  • The compute_PQ_dis_tables_dsub2 kernel is bit-identical to the scalar implementation by construction (no fused multiply-add).

Co-authors

Add vector-length-agnostic RVV implementations of fvec_add (vector and
scalar variants), fvec_sub and compute_PQ_dis_tables_dsub2 for L2 and
inner product. Keep PQ products and the final addition separate.

Introduce AVAILABLE_SIMD_LEVELS_BASE_NO_AVX512 and route the four
dispatchers through it so RVV hosts can select the native kernels.
Enable the PQ dsub=2 path in ProductQuantizer on RISC-V.

Co-authored-by: ihb2032 <hebome@foxmail.com>
Co-authored-by: lyd1992 <liuyudong@iscas.ac.cn>
Co-authored-by: Yuansheng <yuansheng@isrc.iscas.ac.cn>
@meta-cla meta-cla Bot added the CLA Signed label Sep 19, 2026
@meta-codesync

meta-codesync Bot commented Sep 23, 2026

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@mnorris11 has imported this pull request. If you are a Meta employee, you can view this in D121445525.

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2 participants