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Phase 6a: implement original gfx1100 GDN kernels and independent parity gates #46
Description
Scope and ownership
Original gfx1100 GDN GPU execution and parity under the agent-aware program in #150. W7900-only operation remains valid; the second GPU is optional and must be separately qualified. Aletheia owns workload intent; host modes and external service lifecycle remain outside this kernel task.
Verified implementation boundary
Reconciled at main 2d324f92330303ba9eeaa83c4b768550b677bbea.
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feat(kernels): add staged grouped GDN decode step #180 implemented original dense-f32 grouped CPU recurrence/chunk composition and staged one-token HIP GDN. Its native profile is T=1, V<=1024, grouped heads and K-first immutable input state, with separate output/next-state and geometry derived from the existing allocation plan.
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feat(kernels): add staged causal convolution HIP step #181 added staged one-token causal convolution: channel-major oldest-to-newest raw history, separate next-history/output, and an absent history representation for W=1.
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feat: execute native gfx1100 hybrid main models #187 wired those operations into the unsafe blocking native Qwen3.5-family main-model executor, alongside every main full-attention block, embedding, final normalization and distinct output head. Optional NextN auxiliary tensors are not executed.
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feat: refuse invalid native arithmetic before publication #188 added the model-owned sticky numerical-status path. Checked launches classify explicit subnormal/nonfinite inputs and arithmetic results; whole-token synchronization and a clear status read precede logits/state/KV/position publication. Submitted failure poisons the session and uncertain completion retains custody. Raw launchers still retain their declared caller obligations; checked status does not inspect hidden math-library temporaries or qualify denorm behavior.
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Resident/session ownership through feat: own shared native text execution and teardown #192 separates immutable residency, mutable execution and output custody. It does not create a current host grant or safe GPU serving.
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feat(kernels): compose checked packed CPU prefill #194 added checked packed CPU convolution/GDN geometry and composition. feat(decoders): stage native single-sequence recurrent chunks #195 added the bounded native B=1 recurrent row-block consumer.
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feat(decoders): execute bounded native model chunks #196 generalized the native main-model transaction to explicit bounded B=1 chunks: multirow projections, causal multiquery attention, one whole-chunk KV/recurrent/position publication and terminal-only logits. Q1 and chunk attention share one private wave32 numerical body. Legacy constructors retain capacity one.
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feat(hermeneus): execute bounded native prompt chunks #197 consumes exact per-use chunk capacity in Hermeneus's native text adapter. One decoder plan derives execution and device demand; intermediate outputs release before continuation, final-only logits are copied, and cancellation is checked between chunks. No service or scheduler authority is added.
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feat(decoders): publish CPU sequence batches atomically #198 adds the CPU whole-model mixed-sequence transaction/reference owner. It borrows independently positioned executions, preflights every owner's limits and verified model identity, derives cursors from one packed descriptor, stages all recurrent/KV/logit results and prepares every cache append before infallible group publication. Checked live-set accounting distinguishes retained sums, serial workspace maximum and conservative per-owner serialized-backing bounds. It reuses private scalar arithmetic; it is not packed/vectorized device execution.
The merged reviewed heads passed their required CPU/release-kernel, GPU-denial and real HIP archive/code-object/malformed-source checks; exact receipts and limits are recorded on #196 #197, and #198. The latest candidate passed 868 workspace and 178 release-kernel tests; its merged tree is identical and all post-merge checks passed. These are CPU and compiler results, not physical GPU execution. Reserved-device parity remains unrun. Native continuation and late-fault witnesses remain ignored; raw device-state equality and real HIP release are not established. Independent f64 fixtures do not falsify every f32 rounding/FMA/reassociation change; a qualified compiler/math/device profile remains necessary. There is no physical or end-to-end model-quality result.
The old tracker file/line claims, unqualified model-quality fallback claim and instruction to hand-port foreign Triton kernels are not current execution authority. Canonical planning is the private planning corpus; its retired Kanon-tracked copy is not authority. Historical wording remains in this issue's revision history.
Remaining work
- Complete native model-level mixed-sequence ownership and variable-length execution from the landed B=1 chunk path and CPU aggregate reference. The CPU package now witnesses unequal histories/chunks, heterogeneous owner limits/output selections, independent f64 logits/state and later continuation, and bitwise whole-batch rollback with clean retry after a late failure. Native execution still must retain every independent sequence and prepare all cache/state/output publication before any commit; an outer loop over independently committing sessions is insufficient. The CPU private scalar decomposition is not packed/vectorized arithmetic or full S4. Full native acceptance still includes mixed-sequence logits, recurrent/history state, causal attention positions and later continuation. Foreign implementations remain Read-not-Carry evidence, not code/templates/tables to transplant.
- The canonical pinned AITER record now has a bounded non-adoption verdict. Any additional source relied on for remaining kernels needs exact revision/path/licence evidence. Older preflight pins and unresolved line placeholders are not current-pin correctness or gfx1100 support.
- Keep grouped-head mapping, initial/final state, chunk boundaries, input domains and precision explicit. Compose model-specific gating, packing and convolution separately from the generic operation contract.
- Verify with independent CPU oracles and a genuine denied HIP compiler/code-object witness before any hardware execution. Emulation covers only its explicitly supported instruction/domain subset.
- Hardware parity requires an operator-reserved window and exact device, toolchain, artifact, tokenizer/template, corpus and numerical-policy identity. No mode change, incumbent displacement, model forward pass or GPU reservation is authorized by this issue's existence.
Acceptance
The declared GDN APIs execute an original gfx1100 HIP implementation over their supported domain; unsupported inputs fail explicitly. Independent numerical tests cover grouped shapes, state orientation, chunk composition and causality, and required real compilation rejects malformed source.
The original end-to-end parity request (no more than 0.02 PPL divergence on a 1,000-prompt golden set) remains unfulfilled. Its model, tokenizer, corpus and measurement protocol must be pinned and reviewed before it can serve as a qualification gate; a CPU reference or compiler pass is not a substitute. Full native mixed-sequence integration and separately authorized physical qualification remain necessary; the landed B=1 chunk executor and CPU/compiler evidence alone do not establish either.
This issue remains outstanding. See #150 for the wider serving, artifact-admission and fleet-integration acceptance.
Activity
forkwright commentedon Sep 6, 2026
Current-program correction and progress: PR #154 adds original grouped GDN CPU recurrence and a generic causal-convolution CPU reference under the accepted agent-aware implementation plan. The current GDN contract is dense f32, K-first state with precomputed beta/g and explicit grouped-head mapping; independent f64 oracles and all nonempty chunk cuts are tested. This does not satisfy this issue: no GDN HIP kernel, fused Qwen gating/packing adapter, native model execution, or hardware parity has been added. The older file/line claims and model rationale in the original issue body are historical; current implementation/qualification authority is Kanon projects/logismos/IMPLEMENTATION.md and STATE.md. Upstream work is Read-not-Carry reference material, not a porting authorization. Keep this GPU-kernel issue open.
feat: add observation-bound model structure and q8 decoding (#156)
[-]Phase 6a: port chunk_gated_delta_rule + fused_recurrent_gated_delta_rule to HIP WMMA wave32 (gfx1100)[/-][+]Phase 6a: implement original gfx1100 GDN kernels and independent parity gates[/+]forkwright commentedon Sep 8, 2026
Next bounded implementation: an original one-token grouped GDN HIP operation using the existing
kernels::gdngeometry and recurrence owners. It will preserve generic grouped-head mapping (with the separately pre-tiled equal-head Qwen case), natural-log decay, serial f32 reduction order, immutable input state and separate staged output/next-state buffers. The pinned AITER record has a bounded non-adoption verdict; no foreign kernel or dependency is selected.This is a standalone numerical primitive, not active decoder/resident-state integration. Identity-bound hybrid transactions still gate that integration. CPU oracles, typed unsupported-domain refusals and hosted HIP/compiler-object witnesses remain distinct from reserved-device parity. No local device probe, GPU execution, service/mode change or model payload run is part of this increment; #46 stays open for the larger native-domain, prefill and physical/end-to-end acceptance.
forkwright commentedon Sep 8, 2026
The standalone staged grouped decode-step implementation is now in draft #180. Review and exact-head hosted proof live there. It adds a separately ignored reserved-device parity witness, but that witness has not run and establishes no device result merely by existing. This issue remains open for the wider native, prefill and physical/end-to-end acceptance.
feat(kernels): add staged grouped GDN decode step (#180)
feat(kernels): add staged causal convolution HIP step (#181)
feat(kernels): integrate checked paged decode attention (#184)
fix(kernels): avoid packed prefill staging copies
fix(kernels): tighten packed prefill proof fixtures
test(kernels): compare packed state bits
feat(kernels): compose checked packed CPU prefill (#194)
forkwright commentedon Sep 10, 2026
The packed CPU prerequisite landed in #194 at
e6dd128a742a64a8bb1fcc961615f0df90247964. One checked sequence-major descriptor now feeds staged causal convolution, head-major packed GDN, and the existing real B=1 recurrent CPU consumer. Model position/context remains at the model owner; no duplicate recurrent-layer position counter was added.Exact-tree review and CI proof: 831 workspace tests and 163 release-profile kernel tests passed; all 11 PR checks succeeded, including GPU-denial and 13 gfx1100 code-object/malformed-source witnesses. Mixed-length independent f64 arithmetic, partition continuation, late-error bitwise state preservation, overflow/context refusals, and the allocation-owner regression ran. Allocation bounds now exclude the removed copied windows and nested staging aggregates; the report remains logical requested-f32 accounting, not measured process/device capacity.
Next is a complete native multirow recurrent block using those contracts and staged owners, followed by the existing whole-model chunk/KV/logits/continuation and mixed-sequence acceptance. A host loop around T=1 is not that capability. This issue remains open: no native chunk execution, safe serving, real-artifact quality or hardware qualification is claimed, and no GPU/host activity was authorized or performed.
feat(decoders): stage native single-sequence recurrent chunks (#195)
forkwright commentedon Sep 10, 2026
The complete deferred B=1 native recurrent row-block increment is merged in #195 (
be44c41459d252d4fe5cac503d5da1167c35fc84), with reviewed/tested tree equality. It shares batched serialized projections and residual/FFN finish, preserves device-time recurrence order, and owns/accountably retains both V-gather and output-layout buffers. The PR contains exact-head CPU/build/HIP receipts and proof limits.The ignored T=3 complete-block witness compiles but has not run on a GPU. The production main-model path remains T=1. This does not close #46/S4: multirow embedding/logits, causal multiquery attention, whole-chunk KV/recurrent publication, later decode continuation, and explicit mixed-sequence model ownership remain required. No host/grant/lifecycle or hardware qualification claim follows.
forkwright commentedon Sep 10, 2026
Native whole-model B=1 chunk prefill landed in #196 (main4e2848185e51c2b72b9a4c337d76bf8b5e81b7cd), with the same tree as tested16ef024. One exact capacity plan drives transient workspaces, causal multiquery attention, whole-chunk KV/recurrent publication and terminal logits; legacy constructors remain capacity1. Q1 and B1 share one private wave32 arithmetic body. Gate34502411614 passed855 workspace tests and178 release kernel tests; denied boundary/HIP witness34502410513 and security34502411038 passed. 14gfx1100 code objects/14malformed-source rejections and the external launcher symbol were verified. See PR196 for full receipts and skip counts. Native device witnesses remain ignored/unrun; no hardware, artifact, performance, host-grant or serving qualification. Full mixed-sequence model ownership/S4 remains open. Next bounded consumer is Hermeneus prompt chunking via the exact per-use plan, without a new service or scheduler authority.
forkwright commentedon Sep 10, 2026
#197 landed the exact native text prompt-chunk consumer of #196. Legacy planning remains capacity one; explicit per-use capacity and device demand derive from the same decoder plan. Intermediate outputs release before another chunk, final-only logits are copied, and cancellation is checked at chunk boundaries. Final-candidate CI passed 859 workspace and 178 release-kernel tests, denied boundary, gfx1100 code-object compilation and security; merged main has an identical tree and all post-merge checks passed. These are synthetic CPU/control-flow and compilation witnesses, not real HIP release or hardware qualification.
Next bounded source package is the CPU mixed-sequence model transaction oracle: independently positioned existing owners, complete preflight, all staged states/logits retained, every cache append prepared before any infallible publication. Its initial private scalar decomposition will not be called packed/vectorized arithmetic or full S4. Native B>1 composition and real-GPU qualification remain open.
feat(decoders): publish CPU sequence batches atomically (#198)