feat(gen-verilog): resolve const-name array dimensions before codegen - #2402
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The second half of #2275 was one gate: dimensions spelled as const names ([NUM_MAC_UNITS]MACUnit) never parsed, parse_array_type wants digits, so the AoS declaration emitted a 32-bit reg plus a TODO and every element field access flattened to an unbound identifier. resolve_symbolic_dims substitutes integer-literal module consts into every type and dimension string once, before codegen: mac_units becomes reg [1343:0] with per-element part-select initializers and iverilog elaborates mac.v with ZERO errors for the first time. The folded zero initializer is exact for this literal (all fields zero). Blast radius measured first: 13 specs corpus-wide, 2 under specs/fpga; the 32-module yosys smoke stays 32/32. M5 performed. Closes #2275.
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The Rust backend resolved .len() for ages; Verilog emitted the method call verbatim and iverilog rejected it -- arrays have no methods. One fold covers the three parse shapes the same source text produces (method-kind, call-over-field-access, qualified name); the receiver's length comes from the type registries through parse_array_type, with symbolic dims already resolved by the #2402 pass. mac self-test drops 13 -> 12 elaboration errors; class (2) of #2413 is dead. 32/32 yosys smoke unchanged. M5 performed. Refs #2413.
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Closes #2275. One pass unblocks the whole packed-array machinery for symbolic dims; mac.v elaborates with zero iverilog errors for the first time — the vvp lane's (#2241) blocker module is open. 32/32 yosys smoke; blast radius 13 specs measured before landing.
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