verilog: a zero-length array is not a register of usize::MAX bits (Refs #2566)

[gHashTag]

var notebooks : [0]Notebook is a legal empty list. The packed-array path computes total_width = dims[0] * elem_w — zero — and then total_width - 1 on a usize is 18446744073709551615:

reg [18446744073709551615:0] notebooks;

at exit 0, past every green gate. Two sites (1-D and multi-dimensional) clamped the way range_decl clamps.

650 specs regenerated: 1 file differs, and it is the target. Elaboration 176 vs baseline 176. Corpus ratchet clean. Ledger tightened 2 → 1.

The remaining entry is not a bug

Str { data: [4096]u8; len: u32 }                    = 4096*8 + 32     =    32,800
Map { keys: [64]Str; values: [64]Str; count: u32 }  = 2*64*32800 + 32 = 4,198,432

513 KiB in one packed register. The backend computed it faithfully; the spec asked for something with no hardware form. Whether a type that large should be lowerable is a design decision with a cost — filed with the same question about zero-width types, not decided here. The arithmetic now sits beside the ledger entry so the next reader does not look for a subtraction that is not there.

Three absurd widths, three unrelated mechanisms, two of them bugs. A gate that catches a class catches things outside the class it was written for; the discipline is to find the mechanism for each hit rather than assume the one already fixed.

On scope

Searching for this underflow turned up 96 sites formatting [{}:0] with a bare - 1, against 8 using saturating_sub. That is a candidate list, not a finding: exactly one of the 96 produces a bad width over the corpus, because the rest operate on widths that cannot be zero. Fixing 95 unverifiable sites in a compiler is a change nobody can defend later — the count is recorded, the claim is not.

§96 and §97.

Refs #2566

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PR Dashboard

Generated at: 2026-08-23 20:54:41 UTC

• verilog: a zero-length array is not a register of usize::MAX bits (Refs #2566) #2605 verilog: a zero-length array is not a register of usize::MAX bits (Refs #2566) | Created: 2026-08-23 | Updated: 2026-08-23 | 20 failing / 29 total
• Unbreak FPGA CI and correct two unbacked hardware claims #2081 Unbreak FPGA CI and correct two unbacked hardware claims | Created: 2026-08-11 | Updated: 2026-08-20 | 5 failing / 27 total

Summary

Status	Count
Total Open PRs	2
PRs with Failing Checks	1
PRs with All Checks Green	1
READY	0
FAILING	1
PENDING	0

Seal Status

• ⚠️ STALE -- sha256(compiler.rs)=e6333575ec10 != manifest seal=87e5cbd3ad94.
  The committed NMSE numbers were certified against an older compiler.rs.
  Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).