This Doc is WIP
K3 stands for the RISC-V based K3 SoC from SpacemiT overview It's a successor to their K1 SoC featuring 4 CPU clusters, including 2 X100 clusters (4 cores each), and 2 A100 clusters (4 cores each) -- 16 CPUs in total. The X100 is intended for general purpose compute (H extension + 256 vlen) and A100 for "AI" (no H extension, 1024 vlen). More details in paper
| K3 in CoM260 | K3 Block Diagram |
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Based on my analysis of their OpenSBI patch v2 and rvtrace RFC patch, K3 is similar to K1 in that it's based on some ARM SoC design where SpacemiT just replaced the ARM core with RISC-V and reused many of the fabrics, including the cache coherency manager and trace components. It's not build entirely from ground up.
Refer to README
There're essentially 2 boards that regular users can buy:
- K3 Pico-ITX: good for regular use: available with proper case (NUC alike); decent cooling; SFP+ port.
- K3 CoM260: good for advanced users, debugging: Jetson Orin nano compatible; 12V DC in; JTAG from microSD slot.
If you can't access archive.spacemit.com, This directory has many of the pdfs backed up
There's no official TRM being published yet. Only datasheets and design documents here. They are not enough to do meaningful firmware/driver development, but still better than nothing.
SpacemiT maintains very good documentation of board docs here, including Pico-ITX and CoM260.
Benchmark results from Olaf Bernstein: https://camel-cdr.github.io/rvv-bench-results/