media: ipu7: isys: enable C-PHY port A+B aggregation

[syafiqnizam25]

On IPU7P5 a CSI-2 port with more than two lanes is built by aggregating SoC ports A and B, see ipu7_isys_csi_phy_powerup():

if (!is_ipu7(hw_ver) && lanes > 2 && id == PORT_A) {
        aggregation = true;
        lanes = 2;
}

The trigger is PHY-mode agnostic and the port B gpregs are programmed for both modes, but only ipu7_isys_dphy_config() acts on the aggregation flag. ipu7_isys_cphy_config() accepts the same argument and never reads it, so the two PHY macros are never linked: port B is brought up as an unrelated standalone PHY while port A's CSI-2 controller waits for lanes that never arrive coherently. The result is a permanently corrupt stream.

Mirror the D-PHY sequence in the C-PHY path:

• Set the macro link bit CORE_DIG_RW_COMMON_0[1] on both ports and program the AFE lane forwarding bits in AFE_LANEx_CTRL_2_15[4:3]. D-PHY forces its clock-lane AFE (LANE1) to follower mode on port B; C-PHY has no clock lane, so all AFE lanes carry trio wires on both ports and none is a follower.

• Split the trio count across the aggregated macro. A 4-lane D-PHY port is 5 wire pairs; regrouped as C-PHY that is 3 trios (9 of 10 wires), which is also why ipu7_isys_cphy_config() already reports trios = 3 for the native 4-lane port on full IPU7. Port A's three pairs carry trios 0-1 and port B's two pairs carry trio 2.

• Propagate the rext calibration result to the secondary port. Only port A runs the calibration (ipu7_isys_phy_ready() returns early for id != 0), so without this port B has no valid termination trim. The D-PHY path already does this; the C-PHY path was missing it.

The sensor side must advertise a matching trio count, i.e. three data lanes on the endpoint feeding port A.