LATX: streamline AVX audio hot paths

target/i386/latx/include/env.h

@@ -58,6 +58,12 @@ typedef struct TRANSLATION_DATA {
 
     int curr_top;               /* top value (changes when translating) */
 
+    /*
+     * VEX.128 writes make the architectural YMM high half zero.  With LASX,
+     * defer that zeroing until the high half is observed or the TB exits.
+     */
+    uint16_t ymmh_zero_pending;
+    uint8_t ymmh_zero_defer_disabled;
     /* TODO : support static translation */
     uint8 curr_ir1_skipped_eflags; /* these eflag calculation can be skipped */
                                    /* (because of flag pattern, etc) */

target/i386/latx/include/insts-pattern.h

@@ -51,6 +51,11 @@
 
 #define INSTPTN_OPC_SHR_JCC        0x10000000
 #define INSTPTN_OPC_AND_JCC        0x20000000
+#define INSTPTN_OPC_REPEAT_ADD     0x40000000
+#define INSTPTN_OPC_AVX_SUM3       (-0x7fffffff - 1)
+
+void insts_pattern_repeat_add(TranslationBlock *tb);
+void insts_pattern_avx_sum3(TranslationBlock *tb);
 
 typedef int scan_elem_t;
 

target/i386/latx/include/translate.h

@@ -1607,6 +1607,11 @@ IR2_OPND load_freg128_from_ir1(IR1_OPND *);
 void load_imm_to_ir1_opnd_gpr(IR1_OPND *opnd0, uint64_t imm);
 IR2_OPND load_freg256_from_ir1(IR1_OPND *opnd1);
 void set_high128_xreg_to_zero(IR2_OPND opnd);
+void mark_high128_xreg_zeroed(IR2_OPND opnd);
+void materialize_deferred_ymmh_zero(IR2_OPND opnd);
+void materialize_deferred_ymmh_zeros_now(void);
+void materialize_deferred_ymmh_zeros_for_exit(void);
+void disable_deferred_ymmh_zero_for_tb(void);
 IR2_OPND load_ymm_high128_shadow(int index);
 void store_ymm_high128_shadow(IR2_OPND src, int index);
 void clear_ymm_high128_shadow(int index);

target/i386/latx/optimization/flag-lbt.c

@@ -121,6 +121,10 @@ bool generate_eflag_by_lbt(IR2_OPND dest, IR2_OPND src0, IR2_OPND src1,
     case dt_X86_INS_COMISD:
     case dt_X86_INS_UCOMISS:
     case dt_X86_INS_UCOMISD:
+    case dt_X86_INS_VCOMISS:
+    case dt_X86_INS_VCOMISD:
+    case dt_X86_INS_VUCOMISS:
+    case dt_X86_INS_VUCOMISD:
 #endif
     case dt_X86_INS_AAM:
     case dt_X86_INS_AAD:

target/i386/latx/optimization/flag-reduction.c

@@ -112,7 +112,10 @@ static const IR1_EFLAG_USEDEF ir1_opcode_eflag_usedef[] = {
     FLAG_DEFINE(INVLPG,  __NONE, __NONE, __NONE),
     FLAG_DEFINE(UCOMISD, __NONE, __ALL_EFLAGS, __NONE),
     FLAG_DEFINE(UCOMISS, __NONE, __ALL_EFLAGS, __NONE),
+    FLAG_DEFINE(VCOMISD, __NONE, __ALL_EFLAGS, __NONE),
+    FLAG_DEFINE(VCOMISS, __NONE, __ALL_EFLAGS, __NONE),
     FLAG_DEFINE(VUCOMISD, __NONE, __ALL_EFLAGS, __NONE),
+    FLAG_DEFINE(VUCOMISS, __NONE, __ALL_EFLAGS, __NONE),
     FLAG_DEFINE(IRET,    __NONE, __INVALID, __NONE),
 
     /* Jcc */

target/i386/latx/optimization/hbr.c

@@ -125,6 +125,21 @@ static bool deal_xmm_common(TranslationBlock *tb, IR1_INST *ir1, uint32_t *xmm)
     }
 
     switch (ir1_opcode(ir1)) {
+    /* VEX scalar arithmetic copies bits 127:32 from its first source. */
+    case WRAP(VADDSS):
+    case WRAP(VSUBSS):
+    case WRAP(VMULSS):
+    case WRAP(VDIVSS):
+        src_update_des(ir1, xmm);
+        return true;
+    /* Scalar FMA leaves bits 127:32 of the old destination unchanged. */
+    case WRAP(VFMADD132SS):
+    case WRAP(VFMADD213SS):
+    case WRAP(VFMADD231SS):
+    case WRAP(VFMSUB132SS):
+    case WRAP(VFMSUB213SS):
+    case WRAP(VFMSUB231SS):
+        return true;
     case WRAP(ADDPD):
     case WRAP(ADDPS):
     case WRAP(ADDSUBPD):
@@ -204,6 +219,12 @@ static bool deal_xmm_common(TranslationBlock *tb, IR1_INST *ir1, uint32_t *xmm)
     case WRAP(MOVDQU):
     case WRAP(MOVNTPS):
     case WRAP(MOVNTPD):
+    case WRAP(VMOVUPS):
+    case WRAP(VMOVUPD):
+    case WRAP(VMOVAPS):
+    case WRAP(VMOVAPD):
+    case WRAP(VMOVDQA):
+    case WRAP(VMOVDQU):
         if (!ir1_opnd_is_xmm(des_opnd)) {
             /* src will write to mm. */
             src_no_opt(ir1, xmm);
@@ -225,6 +246,17 @@ static bool deal_xmm_common(TranslationBlock *tb, IR1_INST *ir1, uint32_t *xmm)
             zero_update_des(ir1, xmm);
         }
         return true;
+    /* VMOVSS xmm, m32 clears bits 127:32; stores only read bits 31:0. */
+    case WRAP(VMOVSS):
+        if (!ir1_opnd_is_xmm(des_opnd)) {
+            return true;
+        }
+        if (ir1_opnd_is_mem(src_opnd)) {
+            zero_update_des(ir1, xmm);
+        } else {
+            src_update_des(ir1, xmm);
+        }
+        return true;
     /* need 0 ~ 127 every high bit. */
     case WRAP(PMOVMSKB):
         if (ir1_opnd_is_xmm(src_opnd)) {