Avx correctness

target/i386/latx/include/aot.h

@@ -177,6 +177,7 @@ typedef enum aot_rel_kind {
 
     LOAD_HELPER_TRACE_SESSION_BEGIN,
     LOAD_HELPER_UPDATE_MXCSR_STATUS,
+    LOAD_HELPER_UPDATE_MXCSR,
     LOAD_HELPER_FPATAN,
     LOAD_HELPER_FPTAN,
     LOAD_HELPER_FPREM,

target/i386/latx/include/translate.h

@@ -34,6 +34,11 @@ bool TRANS_FUNC(name)(IR1_INST * pir1)
 #define TRANS_FUNC_GEN(opcode, function) \
 TRANS_FUNC_GEN_REAL(opcode, TRANS_FUNC(function))
 
+#ifdef CONFIG_LATX_AVX_OPT
+void lasx_fp_fix_fma_nan(IR2_OPND result, IR2_OPND src1, IR2_OPND src2,
+                         IR2_OPND src3, bool double_precision, int lanes);
+#endif
+
 /*
  * AVX integer operations that can be evaluated independently in each 128-bit
  * half. The operation token is also used by the LSX implementation generator.

target/i386/latx/ir1/ir1.c

@@ -336,6 +336,9 @@ ADDRX ir1_disasm(IR1_INST *ir1, uint8_t *addr, ADDRX t_pc, int ir1_num, void *pi
     struct la_dt_insn *info;
     uint32_t nop = 0x401f0f;
     uint64_t nop_5 = 0x441f0f;
+    uint8_t vex_w0[15];
+    const uint8_t *original_addr = addr;
+    bool restore_vex_w = false;
     if (((*((uint32_t *)addr)) & 0xf8ffffff) == 0xc81e0ff3) {
         //repleace endbr32/rdsspd with 4 bytes nop, just a temporary solution
         addr = (uint8_t *)&nop;
@@ -351,6 +354,18 @@ ADDRX ir1_disasm(IR1_INST *ir1, uint8_t *addr, ADDRX t_pc, int ir1_num, void *pi
         addr = (uint8_t *)&nop_5;
     }
 #endif
+    /*
+     * Capstone rejects VEX.W=1 for the four AVX string compare opcodes,
+     * although W selects their 64-bit-length form. Decode the equivalent
+     * W=0 encoding, then retain W and the original bytes in IR1.
+     */
+    if (addr[0] == 0xc4 && (addr[1] & 0x1f) == 0x03 &&
+        (addr[2] & 0x85) == 0x81 && addr[3] >= 0x60 && addr[3] <= 0x63) {
+        memcpy(vex_w0, addr, sizeof(vex_w0));
+        vex_w0[2] &= ~0x80;
+        addr = vex_w0;
+        restore_vex_w = true;
+    }
     /* FIXME:the count parameter in cs_disasm is 1, it means we translte 1 insn at a time,
      * there should be a performance improvement if we increase the number, but
      * for now there are some problems if we change it. It will be settled later.
@@ -370,6 +385,11 @@ ADDRX ir1_disasm(IR1_INST *ir1, uint8_t *addr, ADDRX t_pc, int ir1_num, void *pi
         exit(-1);
     }
 
+    if (restore_vex_w) {
+        info->x86.rex |= 0x08;
+        memcpy(info->bytes, original_addr, info->size);
+    }
+
     disassemble_trace_cmp(addr, 15, (uint64_t)t_pc, 1, info, CODEIS64);
 
     ir1->_eflag = 0;

target/i386/latx/sbt/aot.c

@@ -1209,6 +1209,7 @@ static void* relkind_to_fixup_addr[] = {
     [LOAD_VPAES_DEC_TABLES_XV] = (void *)latx_vpaes_dec_tables_xv,
     [LOAD_HELPER_TRACE_SESSION_BEGIN] = trace_session_begin,
     [LOAD_HELPER_UPDATE_MXCSR_STATUS] = update_mxcsr_status,
+    [LOAD_HELPER_UPDATE_MXCSR] = helper_update_mxcsr,
     [LOAD_HELPER_FPATAN] = helper_fpatan,
     [LOAD_HELPER_FPTAN] = helper_fptan,
     [LOAD_HELPER_FPREM] = helper_fprem,

target/i386/latx/translator/tr-avx-cmp.c

@@ -3878,7 +3878,7 @@ bool translate_vcmpss(IR1_INST *pir1)
 	lsassert(ir1_opnd_num(pir1) == 4 &&
 			ir1_opnd_is_imm(ir1_get_opnd(pir1, 3)));
 	lsassert((ir1_opnd_is_xmm(ir1_get_opnd(pir1, 0)) &&
-				ir1_opnd_is_xmm(ir1_get_opnd(pir1, 1))));
+			ir1_opnd_is_xmm(ir1_get_opnd(pir1, 1))));
 	uint8 predicate = ir1_opnd_uimm(ir1_get_opnd(pir1, 3)) & 0x1f;
 	switch (predicate) {
 		case 0:

target/i386/latx/translator/tr-avx-shift.c

@@ -194,7 +194,7 @@ bool translate_vpsrlx(IR1_INST * pir1) {
 
         IR2_OPND count = ra_alloc_itemp();
         IR2_OPND max = ra_alloc_itemp();
-        la_addi_d(max, zero_ir2_opnd, max_count);
+        la_addi_d(max, zero_ir2_opnd, max_count + 1);
         la_vpickve2gr_d(count, src2, 0);
         la_blt(count, max, label_shift);
         la_xvxor_v(dest, dest, dest);