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Codex/pr432 aes vaes master - #490

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xiezyang:codex/pr432-aes-vaes-master
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xiezyang:codex/pr432-aes-vaes-master

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Summary

This PR carries forward #432 on top of current master.

  • key AOT cache files by translator build identity so incompatible generated code is not reused
  • translate AESENC/AESENCLAST and VEX-encoded AES rounds directly
  • translate 256-bit VAES encryption rounds with LASX
  • add instruction-level JIT and AOT tests for AES, VEX AES, and VAES
  • invalidate the AES table-address cache before instruction-pattern translation, preventing a CMP/SBB pattern translation from leaving a stale AES table address in a reused temporary register
  • require hot-AOT AES/VAES tests to observe SEG_AOT_LOADED, so a JIT fallback cannot be reported as a successful AOT-cache run
  • pass the 16-byte AES key-load width to the current page-permission check after rebasing onto master

Validation

  • O1 LATX build passed with instruction-pattern and AVX optimization enabled: ninja -C build-pr432-master-final -j8
  • AES/VAES integration test passed: meson test -C build-pr432-master-final test-aes-vaes-rounds --print-errorlogs
    • Covers AES known-answer and all-byte fixtures, VEX.128 VAES, and VAES.256.
    • Covers JIT, cold AOT, and hot AOT.
    • The hot-AOT run requires SEG_AOT_LOADED.
  • Lative cross-host comparison passed:
    • xzy86 native x86 reference: 4,224/4,224
    • LoongArch LATX result: 4,224/4,224 matched
    • Coverage: AESENC/AESENCLAST, VEX.128 VAESENC/VAESENCLAST, and VAES.256 VAESENC/VAESENCLAST; 66 operand/pattern sequences x 64 initial states.
  • git diff --check upstream/master...HEAD passed.

The full lat-pr-fast suite and pairwise merge checks were not rerun. Validation is scoped to the instructions and code paths changed by this PR.

Checklist

  • I have read CONTRIBUTING.md.
  • Every commit contains a DCO sign-off (git commit -s).
  • I have included relevant build or test results, or explained why they are not applicable.

luzeng87 and others added 9 commits September 15, 2026 11:28
Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Generate AESENC and AESENCLAST with scalar table-based IR2 instead of C helpers, and relocate the AES tables for AOT loading. Preserve memory and aliased round keys and release the consumed memory-address temporary before allocating the seven AES integer temporaries. This avoids corrupting the environment register on memory-source forms.

Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Signed-off-by: Lu Zeng <luzeng87@gmail.com>
Direct AES and VAES round translation reuses a host integer temporary that holds the AES table address across consecutive round instructions. Pattern translation can return before the normal translator and overwrite that temporary, leaving the cache state valid even though the register no longer contains the table address. Reset the cache before attempting pattern translation so the following AES or VAES instruction reloads the correct address.

Add AESENC, VAES XMM, and VAES YMM regressions with an intervening CMP/SBB pattern for both carry outcomes.

Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
The hot AOT phase previously checked only that the guest completed successfully. A rejected cache can fall back to JIT and still produce the expected result, making the test pass without loading AOT code.

When the test-only marker is requested, record the guest path after setting SEG_AOT_LOADED. Require that marker during the hot AOT phase for the AES and VAES integration guests.

Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
Signed-off-by: Zhaoyang Xie <xie_zyang@163.com>
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2 participants