API improvements to 4-way interleaved load/store - #298
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…r_interleaved that returns 4 128-bit vectors. This maps to the real-world usage better (in Vello, all uses of this function save one go through manual split/combine first), eliminates pointless split/combine in x86 implementations, and most importantly allows us to add wrappers for vld3q later which would perform the same operation for RGB rather than RGBA.
Shnatsel
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danderson
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Looks reasonable! I can't comment on Vello's use case obviously, but the linked draft looks like a nice reduction in conversion boilerplate.
LaurenzV
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Looking forward to better AVX2 impls and RGB interleaving!
# Conflicts: # fearless_simd_gen/src/ops.rs
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Change
load_interleaved_128that returns a 512-bit vector toload_four_interleavedthat returns four 128-bit vectors.This maps to the real-world usage better (in Vello, all uses of this function save one go through manual split/combine first), eliminates pointless split/combine in x86 implementations, and most importantly allows us to add wrappers for vld3q later which would perform the same operation for RGB rather than RGBA.
Here's how this change affects vello: linebender/vello#1796
Also supports interleaved load/store for all widths, addressing a part of #297
The implementations are untouched in this PR save for removing redundant split/combine. AVX2 leaves performance on the table because it uses the sse2 unpack tree for most types, but I don't want to write a bespoke implementation for what is just a swizzle. Instead let's merge #276, then I'll add a relaxed version for x86 that doesn't zero out-of-bounds indices (update: that's #304), and then we'll just lower interleaving into that on x86 since it would call literally all the same intrinsics.