Allocate NPL controller and host memory from internal RAM - #1
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- Hand the NimBLE controller malloc_internal instead of the untagged malloc - Allocate NPL events, callouts and the msys mbuf pools with calloc_internal - Make ble::malloc_internal available on every chip, not only ESP32/C3/S3
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Fixes peeriot/myrmic#6 (the issue closes once myrmic picks up the new revision of this branch).
On chips with PSRAM (ESP32-C5, C61) the NimBLE controller and the NPL host objects end up in PSRAM, and the controller faults on the first list walk after scanning starts:
compat::malloc::malloc/callocare the untagged esp-alloc C shims (EnumSet::empty()); only the*_internalvariants requestMemoryCapability::Internal. A firmware that registers PSRAM as the first heap region, so that general allocations prefer PSRAM and internal DRAM stays free for tagged callers, therefore puts the controller's memory in PSRAM. The ESP32/C3/S3 adapters already hand the controllermalloc_internal; the NPL path for the C5/C6/C61/H2 controllers did not, andble::malloc_internalwas cfg-gated to the older chips.Change
malloc→crate::ble::malloc_internal.calloc→calloc_internal.ble::malloc_internalgated on both controller kinds (bt_controller = "btdm"or"npl") instead of the three btdm chips;ble::malloc, now only used by the btdm adapters, gated tobtdm.freeis unchanged: the esp-alloc shim reads the stored size, so it frees both kinds.Verification (ESP32-C5 rev 1.0, 8 MB PSRAM)
Scaffolded firmware (
myrmic new --firmware=esp32c5), deployed theadapter-ruuvitag-proBLE cell, sentenable; one variable per round:adapter-govee-h5075deployed,enableReceived measurement from A4:C1:38:…: 23.74 °C, 35.0 %, battery 76 %, repeating)Not touched, but the same pattern: the WiFi OS adapter hands the blob the untagged
mallocas well (wifi/os_adapter/mod.rs). WiFi worked in every round above, so it is left for a separate look.Changelog
esp-radio