Lt9611uxd DSI HDMI Bridge for Shikra IQS

Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml

@@ -4,19 +4,23 @@
 $id: http://devicetree.org/schemas/display/bridge/lontium,lt9611.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Lontium LT9611(UXC) 2 Port MIPI to HDMI Bridge
+title: Lontium LT9611(UXC/C/EX/UXD) 2 Port MIPI DSI to HDMI Bridge
 
 maintainers:
   - Vinod Koul <vkoul@kernel.org>
 
 description: |
-  The LT9611 and LT9611UXC are bridge devices which convert DSI to HDMI
+  The LT9611、LT9611UXC、LT9611C、LT9611EX and LT9611UXD
+  are bridge devices which convert DSI to HDMI
 
 properties:
   compatible:
     enum:
       - lontium,lt9611
+      - lontium,lt9611c
+      - lontium,lt9611ex
       - lontium,lt9611uxc
+      - lontium,lt9611uxd
 
   reg:
     maxItems: 1

Documentation/gpu/drm-kms.rst

@@ -206,11 +206,11 @@ Atomic Mode Setting
           style=dashed
           label="Free-standing state"
 
-          "drm_atomic_state" -> "duplicated drm_plane_state A"
-          "drm_atomic_state" -> "duplicated drm_plane_state B"
-          "drm_atomic_state" -> "duplicated drm_crtc_state"
-          "drm_atomic_state" -> "duplicated drm_connector_state"
-          "drm_atomic_state" -> "duplicated driver private state"
+          "drm_atomic_commit" -> "duplicated drm_plane_state A"
+          "drm_atomic_commit" -> "duplicated drm_plane_state B"
+          "drm_atomic_commit" -> "duplicated drm_crtc_state"
+          "drm_atomic_commit" -> "duplicated drm_connector_state"
+          "drm_atomic_commit" -> "duplicated driver private state"
       }
 
       subgraph cluster_current {
@@ -230,7 +230,7 @@ Atomic Mode Setting
           "driver private object" -> "driver private state"
       }
 
-      "drm_atomic_state" -> "drm_device" [label="atomic_commit"]
+      "drm_atomic_commit" -> "drm_device" [label="atomic_commit"]
       "duplicated drm_plane_state A" -> "drm_device"[style=invis]
    }
 
@@ -265,7 +265,7 @@ Taken all together there's two consequences for the atomic design:
   drm_private_state<drm_private_state>`.
 
 - An atomic update is assembled and validated as an entirely free-standing pile
-  of structures within the :c:type:`drm_atomic_state <drm_atomic_state>`
+  of structures within the :c:type:`drm_atomic_commit <drm_atomic_commit>`
   container. Driver private state structures are also tracked in the same
   structure; see the next chapter.  Only when a state is committed is it applied
   to the driver and modeset objects. This way rolling back an update boils down

Documentation/gpu/komeda-kms.rst

@@ -367,7 +367,7 @@ So, one KMS-Obj represents a sub-pipeline of komeda resources.
 So, for komeda, we treat KMS crtc/plane/connector as users of pipeline and
 component, and at any one time a pipeline/component only can be used by one
 user. And pipeline/component will be treated as private object of DRM-KMS; the
-state will be managed by drm_atomic_state as well.
+state will be managed by drm_atomic_commit as well.
 
 How to map plane to Layer(input) pipeline
 -----------------------------------------
@@ -416,7 +416,7 @@ Add :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pip
         ...
     }
 
-Tracking component_state/pipeline_state by drm_atomic_state
+Tracking component_state/pipeline_state by drm_atomic_commit
 -----------------------------------------------------------
 
 Add :c:type:`drm_private_state` and user to :c:type:`komeda_component_state`,
@@ -454,7 +454,7 @@ similar, usually including the following steps:
                   put the data flow into next stage.
          Setup 2: check user_state with component features and capabilities to see
                   if requirements can be met; if not, return fail.
-         Setup 3: get component_state from drm_atomic_state, and try set to set
+         Setup 3: get component_state from drm_atomic_commit, and try set to set
                   user to component; fail if component has been assigned to another
                   user already.
          Setup 3: configure the component_state, like set its input component,

Documentation/gpu/todo.rst

@@ -120,24 +120,24 @@ Contact: Simona Vetter, respective driver maintainers
 
 Level: Advanced
 
-Rename drm_atomic_state
+Rename drm_atomic_commit
 -----------------------
 
 The KMS framework uses two slightly different definitions for the ``state``
 concept. For a given object (plane, CRTC, encoder, etc., so
 ``drm_$OBJECT_state``), the state is the entire state of that object. However,
-at the device level, ``drm_atomic_state`` refers to a state update for a
+at the device level, ``drm_atomic_commit`` refers to a state update for a
 limited number of objects.
 
 The state isn't the entire device state, but only the full state of some
 objects in that device. This is confusing to newcomers, and
-``drm_atomic_state`` should be renamed to something clearer like
+``drm_atomic_commit`` should be renamed to something clearer like
 ``drm_atomic_commit``.
 
 In addition to renaming the structure itself, it would also imply renaming some
-related functions (``drm_atomic_state_alloc``, ``drm_atomic_state_get``,
-``drm_atomic_state_put``, ``drm_atomic_state_init``,
-``__drm_atomic_state_free``, etc.).
+related functions (``drm_atomic_commit_alloc``, ``drm_atomic_commit_get``,
+``drm_atomic_commit_put``, ``drm_atomic_commit_init``,
+``__drm_atomic_commit_free``, etc.).
 
 Contact: Maxime Ripard <mripard@kernel.org>
 

MAINTAINERS

@@ -14592,6 +14592,13 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
 F:	drivers/gpu/drm/bridge/lontium-lt8912b.c
 
+LONTIUM LT9611C MIPI DSI TO HDMI BRIDGE
+M:	Sunyun Yang <syyang@lontium.com>
+M:	Mohit Dsor <mohit.dsor@oss.qualcomm.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml
+F:	drivers/gpu/drm/bridge/lontium-lt9611c.c
+
 LOONGARCH
 M:	Huacai Chen <chenhuacai@kernel.org>
 R:	WANG Xuerui <kernel@xen0n.name>

arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts

@@ -9,6 +9,7 @@
 #include "shikra-evk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 
 / {
 	model = "Qualcomm Technologies, Inc. Shikra IQS EVK";
@@ -27,6 +28,17 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	hdmi-connector {
+                compatible = "hdmi-connector";
+                type = "a";
+
+                port {
+                        hdmi_con: endpoint {
+                                remote-endpoint = <&lt9611_out>;
+                        };
+                };
+        };
+
 	sound {
 		compatible = "qcom,shikra-iqs-sndcard";
 		model = "shikra-iqs-evk";
@@ -104,6 +116,25 @@
 		regulator-always-on;
 	};
 
+        vreg_lt9611_vcc: regulator-lt9611-vcc {
+                compatible = "regulator-fixed";
+                regulator-name = "lt9611_vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                pinctrl-0 = <&hdmi_reg_en>;
+                pinctrl-names = "default";
+        };
+
+        vreg_lt9611_vdd: regulator-lt9611-vdd {
+                compatible = "regulator-fixed";
+                regulator-name = "lt9611_vdd";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
 	vreg_wlan_3p3_dummy: regulator-wlan-3p3-dummy {
 		compatible = "regulator-fixed";
 		regulator-name = "wlan_3p3_dummy";
@@ -314,6 +345,77 @@
 	firmware-name = "qcom/shikra/a704_zap.mbn";
 };
 
+&i2c4 {
+        status = "okay";
+
+        lt9611uxd: lt9611uxd@41 {
+                compatible = "lontium,lt9611uxd";
+                reg = <0x41>;
+                interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>;
+                reset-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>;
+                vcc-supply = <&vreg_lt9611_vcc>;
+                vdd-supply = <&vreg_lt9611_vdd>;
+
+                pinctrl-0 = <&lt9611_irq_pin &lt9611_rst_pin>;
+                pinctrl-names = "default";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+
+                                lt9611_a: endpoint {
+                                        remote-endpoint = <&mdss_dsi0_out>;
+                                };
+                        };
+
+                        port@2 {
+                                reg = <2>;
+
+                                lt9611_out: endpoint {
+                                        remote-endpoint = <&hdmi_con>;
+                                };
+                        };
+                };
+        };
+};
+
+&mdss {
+        status = "okay";
+};
+
+&mdss_dsi0 {
+        vdda-supply = <&pm8150_l11>;
+
+        status = "okay";
+};
+
+&mdss_dsi0_out {
+        remote-endpoint = <&lt9611_a>;
+        data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0_phy {
+        status = "okay";
+};
+
+&pm8150_gpios {
+        hdmi_reg_en: hdmi-reg-en-state {
+                pins = "gpio4";
+                function = PMIC_GPIO_FUNC_NORMAL;
+                bias-disable;
+        };
+};
+
+&pm8150_l11 {
+        /* DSI VDDA - must be at NOM voltage for PHY PLL lock */
+        regulator-min-microvolt = <1232000>;
+        regulator-max-microvolt = <1232000>;
+        regulator-allow-set-load;
+};
+
 &i2c3 {
 	status = "okay";
 
@@ -588,6 +690,20 @@
 		bias-disable;
 	};
 
+	lt9611_irq_pin: lt9611-irq-state {
+		pins = "gpio85";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	lt9611_rst_pin: lt9611-rst-state {
+		pins = "gpio76";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
 	max98091_default: max98091-default-state {
 		pins = "gpio28";
 		function = "gpio";

arch/arm64/configs/defconfig

@@ -971,6 +971,7 @@ CONFIG_DRM_LONTIUM_LT8713SX=m
 CONFIG_DRM_LONTIUM_LT8912B=m
 CONFIG_DRM_LONTIUM_LT9211=m
 CONFIG_DRM_LONTIUM_LT9611=m
+CONFIG_DRM_LONTIUM_LT9611C=m
 CONFIG_DRM_LONTIUM_LT9611UXC=m
 CONFIG_DRM_ITE_IT66121=m
 CONFIG_DRM_NWL_MIPI_DSI=m

drivers/gpu/drm/adp/adp_drv.c

@@ -128,7 +128,7 @@ struct adp_drv_private {
 #define crtc_to_adp(x) container_of(x, struct adp_drv_private, crtc)
 
 static int adp_plane_atomic_check(struct drm_plane *plane,
-				    struct drm_atomic_state *state)
+				    struct drm_atomic_commit *state)
 {
 	struct drm_plane_state *new_plane_state;
 	struct drm_crtc_state *crtc_state;
@@ -150,7 +150,7 @@ static int adp_plane_atomic_check(struct drm_plane *plane,
 }
 
 static void adp_plane_atomic_update(struct drm_plane *plane,
-				    struct drm_atomic_state *state)
+				    struct drm_atomic_commit *state)
 {
 	struct adp_drv_private *adp;
 	struct drm_rect src_rect;
@@ -192,7 +192,7 @@ static void adp_plane_atomic_update(struct drm_plane *plane,
 }
 
 static void adp_plane_atomic_disable(struct drm_plane *plane,
-				     struct drm_atomic_state *state)
+				     struct drm_atomic_commit *state)
 {
 	struct adp_drv_private *adp = to_adp(plane->dev);
 
@@ -278,7 +278,7 @@ static void adp_crtc_disable_vblank(struct drm_crtc *crtc)
 }
 
 static void adp_crtc_atomic_enable(struct drm_crtc *crtc,
-				   struct drm_atomic_state *state)
+				   struct drm_atomic_commit *state)
 {
 	struct adp_drv_private *adp = crtc_to_adp(crtc);
 
@@ -291,7 +291,7 @@ static void adp_crtc_atomic_enable(struct drm_crtc *crtc,
 }
 
 static void adp_crtc_atomic_disable(struct drm_crtc *crtc,
-				    struct drm_atomic_state *state)
+				    struct drm_atomic_commit *state)
 {
 	struct adp_drv_private *adp = crtc_to_adp(crtc);
 	struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
@@ -307,7 +307,7 @@ static void adp_crtc_atomic_disable(struct drm_crtc *crtc,
 }
 
 static void adp_crtc_atomic_flush(struct drm_crtc *crtc,
-				  struct drm_atomic_state *state)
+				  struct drm_atomic_commit *state)
 {
 	u32 frame_num = 1;
 	unsigned long flags;

drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

@@ -128,19 +128,19 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
 };
 
 static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc,
-					   struct drm_atomic_state *state)
+					   struct drm_atomic_commit *state)
 {
 	drm_crtc_vblank_on(crtc);
 }
 
 static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc,
-					    struct drm_atomic_state *state)
+					    struct drm_atomic_commit *state)
 {
 	drm_crtc_vblank_off(crtc);
 }
 
 static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
-					  struct drm_atomic_state *state)
+					  struct drm_atomic_commit *state)
 {
 	unsigned long flags;
 	if (crtc->state->event) {
@@ -260,13 +260,13 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = {
 };
 
 static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane,
-					    struct drm_atomic_state *old_state)
+					    struct drm_atomic_commit *old_state)
 {
 	return;
 }
 
 static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane,
-					  struct drm_atomic_state *state)
+					  struct drm_atomic_commit *state)
 {
 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 										 plane);