Dual-core 16-bit RISC processor
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Updated
Jul 21, 2024 - VHDL
Dual-core 16-bit RISC processor
In this project we implemented a slightly modified version of Space Invaders on an FPGA.
Simple VGA demo based on Digilent Basys2 eval board (Xilinx Spartan-3E XC3S100E-4CP132)
🚨 FCT NOVA · Logic Systems (SL), 2022/23: a synchronous alarm circuit (datapath + Moore control unit) designed in Xilinx ISE, tested with VHDL and run on a Basys 2 FPGA.
Verilog implementation of an incremental memory system and FPGA seat reservation system
CPU de 8 bits com acumulador + RAM 8x8, implementadas em VHDL no Vivado.
Micro Electronics Lab 2022
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