coverage-driven-verification

Here are 4 public repositories matching this topic...

dhruvalmistry2007 / systemverilog-assertions-functional-coverage-framework

Reusable SystemVerilog verification framework that pairs immediate and concurrent assertions with functional coverage. Protocol and reset checks flag violations at the exact failing cycle, while covergroups, coverpoints and cross coverage show which scenarios the tests still miss. Checkers attach to any design through bind.

asic verification assertions systemverilog gtkwave vlsi verilator sva design-verification functional-coverage covergroup rtl-verification protocol-checker coverage-driven-verification cross-coverage concurrent-assertions

Updated Nov 4, 2026

chitti-learns-ai / verif-kit

Star

Independent, coverage-driven verification for any project — spec-kit, but for verification. A blind AI agent verifies your code from the spec alone, with reproducible bug-injection evidence (20/20 catchable bugs detected across 22 cases).

testing mutation-testing verification property-based-testing metamorphic-testing ivv ai-agent claude-code spec-driven-development coverage-driven-verification

Updated May 26, 2026
TypeScript

anisettisathvik / ddr4-controller-verification

Star

DDR4-2400 controller with an independently-reasoned reference model, bound timing assertions, functional coverage with derived unreachable bins, a 15-mutation score, and a search-vs-LLM coverage-closure benchmark.

mutation-testing systemverilog uvm functional-verification memory-controller hardware-verification rtl-design ddr4 coverage-driven-verification

Updated Sep 11, 2026
SystemVerilog

Mohank-VLSI-Verification / sv-verification-portfolio

Star

UVM-based verification portfolio for APB, AXI, I2C, SPI, and UART protocols. Class-based testbenches with sequence library, reference model, dual TLM-FIFO scoreboard, functional coverage (uvm_subscriber), SVA assertions, and Makefile/TCL build flow.

i2c spi tlm uart constrained-random xilinx-vivado axi amba apb asic-verification design-verification functional-coverage uvm-verification assertion-based-verification reference-model coverage-driven-verification

Updated Jul 1, 2026
SystemVerilog

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