misr

Enhance low resolution image using Convolutional Neural Nets. My solution to European Space Agency's one of its many contest.

VHDL circuit testing project featuring scan-based TRCUT architecture with testbenches, LFSR-based pseudorandom input generation, MISR-based signature analysis with fault injection (stuck-at and transient), and full IEEE 1149.1 (JTAG) implementation with TAP controller and boundary scan.

Detecting daytime clouds in the arctic 🌨

Analysis of nearly-coincident cloud top height (CTH) Level 2 data from MISR and MODIS on-board NASA's Terra satellite and ISS-CATS to validate passive sensor products.

Built-In Self-Test (BIST) ALU implemented in Verilog with LFSR and MISR.

A comprehensive Verilog implementation of modern hardware testing architectures, featuring DFT (Scan Chains), BIST (LFSR/MISR), and the IEEE 1149.1 JTAG standard.

BIST for 4-bit adder using LFSR & MISR (Verilog).