Three Verilog-based MIPS CPU projects, simulate pipelined cpu based on mips instruction set:single-cycle, multi-cycle, and a microsystem based on the multi-cycle cpu.
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Apr 24, 2021 - Verilog
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multi-cycle-cpu
Here are 7 public repositories matching this topic...
Single and Multi-cycle ARM processors implemented using VHDL
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Jan 26, 2021 - VHDL
Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor
processor-architecture arm processor verilog mcu computer-architecture hazard-detection pipeline-processor verilog-hdl 32-bit arm32 pipline processor-design single-cycle-processor multi-cycle-processor multi-cycle-cpu datapath-design
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Jun 28, 2024 - Verilog
A multi-cycle CPU which supports 54 Mips instructions
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Jul 13, 2023 - Verilog
OAC - Grupo B3 - Lucas Santana e Gabriel Castro (CIC0099 - UnB 2025/1)
cpu vhdl riscv hdl modelsim risc-v unb oac quartus pipeline-cpu harware multi-cycle-cpu uni-cycle-cpu
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Jul 14, 2025 - VHDL
MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy
mips vhdl computer-organization hardware-design multi-cycle-cpu single-cycle-cpu pipelined-processor-design
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Dec 18, 2025 - VHDL
A Simple 8-bit Multi-Cycle CPU design and implementation using Logisim. Includes a custom datapath, ALU, and hardwired control logic.
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Feb 21, 2026
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