platform-designer

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Matrix multiplication on multiple Nios II cores

fpga parallel-computing matrix-multiplication verilog mailbox nios shared-memory hdl fpga-soc qsys parallel-programming nios2 de2-115 quartus spmd sopc platform-designer

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

arm cryptography encryption fpga verilog altera systemverilog hdl soc chacha20 dma cyclone-v ip-core hps rfc7539 platform-designer rfc8439

PERIDOT Standard peripherals

qsys quartus-prime peridot platform-designer

Codex skill for end-to-end, version-aware Intel/Altera FPGA and SoC engineering with Quartus, Platform Designer, timing, programming, HPS, and CI.

fpga systemverilog quartus intel-fpga platform-designer codex-skill

NIOSV + ws2812b_mm

bsp ws2812b quartus-prime platform-designer cyclone10lp niosv

FPGA/SoPC review lab repository covering Quartus, Platform Designer/Qsys, Verilog custom IP, Avalon-MM and Nios II C.

fpga embedded-systems verilog custom-ip quartus hardware-software sopc nios-ii platform-designer avalon-mm

DE10-Standard Cyclone V SoC Ethernet controller with PC and Android TCP clients, HPS Linux, PIO bridge access, and HEX display output.

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