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Veda sparse attention for ComfyUI's MiniMax-H3, with a hand-written CUDA kernel for NVIDIA Turing (sm_75) so it runs on RTX 2080 Ti / GTX 16-series and any compute-capability 7.5 card. Upstream Veda only supports SM80+. Measured on one 2080 Ti: 4.16x at 768x768x124, 1.83x at 512x512x124.
Compiler MVP that detects Transformer fusion patterns, generates optimized CUDA kernels with WMMA Tensor Cores, and executes them on real GPU hardware — 10.5 TFLOPs on RTX 2070, correctness validated against PyTorch.
Backward pass CUDA kernels for fused GEMM+Bias+GeLU on SM75 (Turing). Float4 vectorized WMMA kernels validated against PyTorch autograd. 3.1x faster than autograd at M=1024. 24/24 tests passing.
MX450 (TU117) has no Tensor Core in silicon — a reproducible reverse-engineering case study: Falcon microcode, register-level proofs, and why every HMMA library is 18x slower. 三语文档。
Fork of vLLM carrying the SM75 / Qwen3.8 changes used by qwen3-8-27b-dual-2080ti-vllm (branch 2080ti_dual_qwen38-27B); upstream main is kept as the 'upstream' branch