verilo

Basic JTAG standard implementation in Verilog and integration with a CUT

Police Simulator game using FPGA with mouse, mp3, vga (Vivado and Verilog). FPGA实现，鼠标，MP3，VGA显示器。

This is my HDL code page which I started to showcase my coding skills and documenting my work for future reference. I am pursuing my master's at Texas A&M University (2019-21). I am looking forward to be a verification engineer. If you have any doubts you are welcomed to email me @ arunraja08@gmail.com

Coroutine simulation engine for verilator

RTL implementation of a 6-State Traffic Light Controller using Verilog HDL with functional simulation and verification.