Cortex-M: add compiler fences to interrupt enable/disable asm

[Copilot]

Cortex-M interrupt toggling used inline cpsie i / cpsid i without a compiler memory clobber, allowing surrounding memory operations to be reordered by the optimizer. This aligns the implementation with expected compiler-fence semantics for IRQ state transitions.

• What changed

  • Updated core/src/cpus/cortex_m.zig interrupt primitives to include a "memory" clobber on both global IRQ control instructions.

• Why this matters

  • Ensures memory accesses are not moved across interrupt enable/disable boundaries by the compiler.

• Code update

  pub fn enable_interrupts() void {
      asm volatile ("cpsie i" ::: "memory");
  }
  
  pub fn disable_interrupts() void {
      asm volatile ("cpsid i" ::: "memory");
  }

• Fixes [CPU: Cortex-M] Missing compiler fences in the interrupt code? #992

[Grazfather]

@copilot Use the new clobber syntax:
https://ziglang.org/documentation/master/#toc-Assembly

.{ .memory = true}

[Copilot]

@copilot Use the new clobber syntax:
https://ziglang.org/documentation/master/#toc-Assembly

...

Updated in commit 314fb60 to use the new clobber syntax for both Cortex-M IRQ helpers: asm volatile ("cpsie i" ::: .{ .memory = true }); and asm volatile ("cpsid i" ::: .{ .memory = true });.

[g-berthiaume]

Thanks!